We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Internet Explorer 11,
Safari. Thank you!
AR# 64093: LogiCORE CPRI v8.3 - Master sends a reset if HDLC set to "0"
LogiCORE CPRI v8.3 - Master sends a reset if HDLC set to "0"
In the LogiCORE CPRI v8.3, when Preferred HDLC rate (0xa) is set to 0 and Preferred Ethernet Pointer (0xb) is set to 0 in the Master core, then Received Subchannel 2, Word 2 (0x6), Z.130.0 of the Slave is 1.
The Slave is told to receive a reset.
However, (0xa)=0 and (0xb)=0 indicates Passive Mode.
Passive mode must be run without reset.
Why does the Master send a reset?
The hardware demonstration design from the CPRI evaluation lounge contains the following code:
reset_request <= '1' when stat_code_r /= "1111" else '0';
To avoid sending a reset, the above code should be removed.