We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64103

UltraScale GTH/GTY TX/RX PROG DIV block reset requirements


UltraScale GTH & GTY have a new TX programmable divider (TX PROG DIV) and RX programmable divider (RX PROG DIV) block for clock division.

These blocks have independent asynchronous reset signals TXPROGDIVRESET and RXPROGDIVRESET.

When are these resets expected to be asserted?


Because TXPROGDIVRESET and RXPROGDIVRESET are independent reset signals, GTTXRESET and GTRXRESET do not reset these blocks.

Whenever there is a change or interruption of the input clock or a change of divider value, PROG DIV blocks must be reset using its independent reset signal followed by an overall reset of GTTXRESET or GTRXRESET.

On the TX side, TXOUTCLK is not expected to flatline during a GTTXRESET triggered reset sequence if TXOUTCLKSEL is set to 101 and TX_PROGCLK_SEL is not set to 00. TXOUTCLK will flatline during a GTTXRESET triggered reset sequence and users are expected to reset the TXPROGDIV block through XPROGDIVRESET reset input.

On the RX side, because the input clock to the RXPROG DIV block is from CDR, RXOUTCLk will flatline during GTRXRESET (and also reset CDR) triggered reset sequence.

So, if RXOUTCLKSEL is set to 101 or RXRECCLKOUT is used to send a refclk off the chip, then when GTRXRESET is asserted, the RXPROGDIV block must also be reset through the RXPROGDIVRESET reset input.

AR# 64103
Date Created 03/30/2015
Last Updated 03/23/2016
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Vivado Design Suite - 2015.1
  • UltraScale FPGA Transceiver Wizard