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AR# 64107

2015.2 Vivado IP Flows - Synthesis fails "ERROR: [Synth 8-493] no such design unit 'abc'" when using direct instantiation of IP in non-project mode

Description

When I instantiate Xilinx IP using the direct instantiation method the synthesis fails with the below error in non-project mode:

ERROR: [Synth 8-493] no such design unit 'abc'


The same design works in project mode using the GUI.

Below is the script used in non-project mode.

read_ip abc.xci

generate_target all [get_ips abc]

synth_ip [get_ips abc]

synth_design -top ${TOP} -part ${DEVICE} -mode out_of_context

Solution

This issue is only seen with non-project mode when using OOC synthesis for IP.

The work-around is to disable OOC synthesis for IP when working in non-project mode.

Edit the script as below:

read_ip abc.xci

generate_target all [get_ips abc]

set_property GENERATE_SYNTH_CHECKPOINT FALSE [get_files abc.xci]

synth_design -top ${TOP} -part ${DEVICE} -mode out_of_context


This issue is scheduled to be fixed in Vivado 2015.3.

AR# 64107
Date Created 03/30/2015
Last Updated 07/08/2015
Status Active
Type Known Issues
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2015.2