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AR# 64117

UltraScale - Inter-byte clocking

Description

In UltraScale devices, Quad Byte Clock (QBC) inputs can be used to clock all four bytes in a bank via inter-byte clocking using the CLK_TO_EXT_SOUTH, CLK_TO_EXT_NORTH and CLK_FROM_EXT ports on the BITSLICE_CONTROLs.

If extending from Byte 2 to Byte 0, does the BITSLICE_CONTROL in Byte 1 need to be instantiated?

Solution

When using the QDC in Byte 2, the inter-byte clocking connects to Byte 1 and Byte 3.

From Byte 1, inter-byte clocking can used to clock Byte 0.

 

Therefore, if you are using inter-byte clocking from Byte 2 to Byte 0, then the BITSLICE_CONTROL in Byte 1 needs to be instantiated.

The BITSLICE in the location BITSLICE 0 in Byte 1 needs to be instantiated and set to CLOCK_AND_DATA or DATA.

Note: Once the Bitslice_0 is instantiated the pin is not available for anything else in the design.

 


 

 

This also means that if you are using the QDC in Byte 1 and inter-byte  clocking from Byte 1 to Byte 3, then the BITSLICE_CONTROL in Byte 2 needs to be instantiated.

AR# 64117
Date Created 03/31/2015
Last Updated 11/30/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale