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AR# 64127

v5.0 AXI_CAN: Does not support the AXI_WSTRB signal


I am using the AXI_CAN IP block in a system and I want to write the AXI_Lite registers 16-bits at a time. 

In simulation, it appears that the AXI_WSTRB signals are ignored and all 32-bits of the register are written with each write.

In a number of AXI peripherals, there is a parameter called C_USE_WSTRB that controls this function in the AXI_LITE_IPIF block.

Is this parameter supported for the AXI_CAN IP?


C_USE_WSTRB is not used for this core.

The documentation will be updated to reflect this.

AR# 64127
Date Created 04/01/2015
Last Updated 04/17/2015
Status Active
Type General Article
  • SoC
  • FPGA Device Families