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AR# 64138

2015.2: Vivado simulator not honoring concurrent assert statement when there is time expression (NOW)

Description

I am trying to use a concurrent assert statement, but Vivado 2015.2 simulator is not displaying a report message even when the condition is true.

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity testbench is
end testbench;

architecture behavioural of testbench is
signal tb_counter : integer := 0;
begin

tb_counter <= tb_counter + 1 after 1 ns;
process(tb_counter)
begin
end process;
assert not(tb_counter mod ((2**20)-1) = 0 and NOW /= 0 ps)
report "maximal length detected at lfsr at the correct time/code - YIPEE!"
severity NOTE;
end behavioural;

Solution

This problem has been fixed in Vivado 2015.3. There is an issue in evaluating expression with time during concurrent assertion.

The work-around is to use sequential assert statements and avoid using concurrent asserts.

process(tb_counter)
begin

assert not(tb_counter mod ((2**20)-1) = 0 and NOW /= 0 ps)
report "maximal length detected at lfsr at the correct time/code - YIPEE!"
severity NOTE;

end process;

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
63956 2015.x Vivado Simulator - Known Issues N/A N/A
AR# 64138
Date Created 04/02/2015
Last Updated 01/06/2016
Status Active
Type General Article
Devices
  • FPGA Device Families
Tools
  • Vivado Design Suite - 2015.2
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2014.4.1
  • More
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.3
  • Vivado Design Suite - 2014.2
  • Vivado Design Suite - 2014.1
  • Less