We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64139

What Do I Do If My Simulation Fails?


When I am running Simulation, it is sometimes unclear what to do if it fails. 

The Tcl console and the Vivado log might not contain sufficient information to debug the issue.



This Answer Record illustrates the immediate steps you can try if the Simulation fails.

As soon as the Simulation fails at any stage in Vivado Simulator, browse over to the Simulation Run directory which will be similar to the following:


(where sim_stage could be - behav, synth, or impl.)

There are three files which can be referred to for Errors.

They are:

  • compile.log - This is the log for xvhdl & xvlog and contains Errors from the compilation stage.
  • elaborate.log - This is the log for xelab and contains Errors from the elaboration stage.
  • simulate.log - This is the log for xsim and contains Errors from the simulation stage.

Once you have found the errors in these files, you need to work towards fixing them.

For more help, please create a Webcase with the testcase and log files or post in the Xilinx Forums.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58799 Xilinx Simulation Solution Center - Design Assistant - Vivado Simulator N/A N/A
AR# 64139
Date Created 04/02/2015
Last Updated 04/14/2015
Status Active
Type General Article
  • Vivado Design Suite - 2015.1