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AR# 64142

Vivado IPI - AXI Ethernet Subsystem v6.2 or earlier - UltraScale SGMII over LVDS - Synchronization and reset issue


When using AXI Ethernet on an UltraScale device with SGMII over LVDS, synchronous SGMII is not stable.

There are synchronization and reset issues.

This Answer Record contains the steps to resolve this for a core generated in a BD design. 

For AXI Ethernet generated in IP Catalog, please refer to (Xilinx Answer 63914).


An AXI Ethernet SGMII over LVDS design with the option "Shared Logic in Example Design" requires an idelay control element which is not currently present in the IPI catalog.
As a result you will need to add this idelay control element as a local pcore and then make the connection.
Below are the steps to follow:
1)      Add a util_idelay control element as a local pcore.
2)      Create the system as required in IPI.
3)      Assign addresses in the address editor.
4)      Save the bd design and validate the bd design to ensure that there are no errors or warnings.
5)      Add the idelay element in the IPI design.
6)      Connect a 625MHz clock to the idelay control element.
7)      Instantiate proc sys reset and generate a reset synchronous to the 625MHz clock then connect it to the idelay control reset input.
8)      Save the bd design.
9)      Run "generate output products" and create the wrapper commands.
10)   Lock the bd. There is a check box to do this in the properties tab of the bd.
       This prevents Vivado from over writing the edited files.
11)   Apply changes in serdes_1_to_10_ser8.v and the wrappers as mentioned in the Answer records below:
a.       as per (Xilinx Answer 62072),
Connect 1b0 to enable_monitor of delay_controller_wrap in _serdes_1_to_10_ser8.v              
b.      Make the changes in (Xilinx Answer 63844)

i.      Update the generated serdes_1_to_10_ser8.v file with the below changes:

Add a reset synchronizer on reset, synchronized to rxclk_div4 clock.
Connect reset_sync to thr RST pin of the following module instances:
  • idelay_m
  • idelay_s
  • idelay_cal
Remove connection of EN_VTC to ~idelay_rdy and tie it instead to 1b0 for following module instances:
  • idelay_m
  • idelay_s
  • idelay_cal

ii.      Propagate idelay_rdy from the top level to serdes_1_to_10_ser8, all the way through the generated wrappers.

That is to the input port <ethernet instance>/inst/pcs_pma/inst/lvds_transceiver_mw/serdes_1_to_10_ser8_i/idelay_rdy in the lvds_transceiver_ser8.v file.
12)   Run synthesis and the rest of the flow.


AR# 64142
Date Created 04/02/2015
Last Updated 04/30/2015
Status Active
Type General Article
  • Zynq-7000
  • Artix-7
  • Kintex-7
  • More
  • Virtex UltraScale
  • Kintex UltraScale
  • Virtex-7
  • Less
  • Vivado Design Suite - 2015.1
  • AXI Ethernet