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AR# 64149

2015.1 Vivado IP Flows - UltraScale GT is not creating the clocks rxoutclk or txoutclk in the IP core's OOC run

Description

I have created an UltraScale GT IP core using the GT wizard. 

When I generate target files for the IP core, if OUT Of Context (OOC) generation is selected, the constraints that create the rxoutclk and txoutclk clocks are not applied.

I need the clocks to be generated in order to apply timing constraints to them.

For Example:

I am trying to apply a constraint to the clocks by running the command below but the get_clocks command returns an empty list.

get_clocks -of_objects <GT output pin(s)>

Solution

In Vivado 2015.1, if a generated clock source does not drive anything, Vivado does not create the generated clock.

If the GT IP core is synthesized in OOC mode, the rxoutclk and txoutclk do not drive any other components. 

Therefore, these clocks are not generated.

As a result, the <IP_name>_in_context.xdc file which is created at the end of the IP OOC run does not contain these generated clocks which are required for timing constraints.


An enhancement has been requested to generate clocks for output clock ports for an OOC synthesis run.
 
Either of the following options can be used to work around this issue for the GT UltraScale IP:
 
  • Turn off OOC for the GT Wizard so that the generated clocks get created on rxout and txout
     
  • Make a user level XDC file marked for synthesis only and place before any XDC that needs to make reference to the rxout or txout clock.
    The XDC should contain create_clock commands for the rxout and txout clock if they are used by the user.
    This forces them to create synthesis-only clock objects on the IP black box outputs.

This issue will be fixed in Vivado 2015.2.

AR# 64149
Date Created 04/02/2015
Last Updated 04/30/2015
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2015.1