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AR# 64153

Virtex-7 Gen3 Integrated Block Wrapper for PCI Express - PCIE_ASYNC_EN is not set correctly for Asynchronous Clocking


Version Found: v3.0 (Rev4)

Version Resolved and other Known Issues: See (Xilinx Answer 54645)

When "Slot Clock Enable" in the Core Configuration GUI is unchecked for Asynchronous Clocking, PCIE_ASYNC_EN is not set correctly in the generated wrapper files.

PCIE_ASYNC_EN must be set to TRUE for Asynchronous Clocking and FALSE for Synchronous Clocking.


This is a known issue to be fixed in a future release of the core. 

Please install the patch attached with this answer record, as described below.

  •     This patch is for Vivado 2014.4.1
  •     Unzip the attached zip file to the directory of your choice.
  •     Open Vivado 2014.4.1 and create a new project.
  •     Open IP catalog. Right click the core you are using and choose IP Settings.
  •     Click Add Repositories and point it to the location where you have unzipped the patch.
  •     Click OK and you are now ready to generate the core.
  •     If you have previously generated the core, you can choose 'Upgrade IP' on your core.
  •     Alternatively, you can use the MYVIVADO environment variable and point this to the location of the patch.

After the patch is installed, the version of the core should indicate: v3.0 (Rev. 5).

Note: "Version Found" refers to the version where the problem was first discovered. 

The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:
04/07/2015 - Initial Release


Associated Attachments

Name File Size File Type
AR64153_Vivado_2014_4.1_preliminary_rev1.zip 717 KB ZIP
AR# 64153
Date Created 04/02/2015
Last Updated 06/15/2015
Status Active
Type Known Issues
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)