# Both clka and clkb are clocks on the FPGA pads. They are two clocks that are locked by external PLL on board.
#clkb's frequency is a half of clka and is ahead of clka by 11ns
NET "clka" TNM_NET = "clka";
TIMESPEC TS_clka = PERIOD "clka" 24.576 MHz INPUT_JITTER 50 ps;
NET "clkb" TNM_NET = "clkb";
TIMESPEC TS_clkb = PERIOD "clkb" TS_clka / 2 PHASE -11 ns INPUT_JITTER 2 ns;
# the offset in is associated to clkb, 15ns is the time difference between the start of data valid window and the capturing rising clock edge of clkb
NET "data" OFFSET = IN 15 ns VALID 30 ns BEFORE "clkb" RISING;