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AR# 64175

2014.4 Virtex UltraScale - Clock placement error [Place 30-716] when driving two MMCMs from one port

Description

The following error occurs when driving two MMCMs from a single port.
 
ERROR: [Place 30-716] Sub-optimal placement for a global clock-capable IO pin-BUFGCE-MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
 
< set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets port_clocking_inst/lopt] >
 
port_clocking_inst/BUFGCE (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y168 (in SLR 1)
port_clocking_inst/sys_mmcm0_inst/inst/mmcme3_adv_inst (MMCME3_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME3_ADV_X0Y6 (in SLR 1)
port_clocking_inst/sys_mmcm1_inst/inst/mmcme3_adv_inst (MMCME3_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME3_ADV_X0Y8 (in SLR 1)

Solution

The error occurs because each clock region contains only one MMCM and so it is necessary for one of the MMCMs to be placed in a separate clock region using the following configuration:
 
1) The IBUFDS should drive one MMCM directly in the same clock region.
 
2) The IBUFDS should also drive a BUFGCE to drive the other MMCM in another clock region.
 
3) Set the following property to allow the necessary backbone routing:
 

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets port_clocking_inst/clk_100m_bufgce]

AR# 64175
Date Created 04/06/2015
Last Updated 04/16/2015
Status Active
Type General Article
Devices
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2014.4