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AR# 64176

Vivado UltraScale Partial Reconfiguration - DRC (HDPR-50) still occurs even if all BUFGCE/MMCM_ADV ranges in the clock range are added into Reconfigurable Module's pblock

Description

In my partial reconfiguration design, BUFGCE/MMCM_ADV components are included in the reconfigurable module, so I add all of the BUFGCE/MMCM_ADV range in the clock range into the RM's pbocks when floorplanning.

However, I still get the following error message during opt_design:

ERROR: [Drc 23-20] Rule violation (HDPR-18) No Pblock range for cell - HD.RECONFIGURABLE primitive cell 'XX' is not ranged by Pblock '<pblock_name>'. A reconfigurable Pblock must range all of its cell primitive types. A 'BUFGCE' range needs to be added to the Pblock.
ERROR: [Drc 23-20] Rule violation (HDPR-50) Programmable Unit missing range - HD.RECONFIGURABLE primitive cell 'XX' is not ranged by Pblock '<pblock_name>'. A reconfigurable Pblock must range all of its cell primitive types.
SNAPPING_MODE is set on this Pblock. Although site range 'BUFGCE' is included in the Pblock, it is removed by SNAPPING_MODE because other site ranges required by the programmable unit are missing or not created correctly. Please ensure required site types in the programmable unit are ranged correctly.

How can I resolve this issue?

Solution

These two error messages are reasonable.


The BUFGCE range is actually in the pblock GRID_RANGES as added by the user. 

The problem is that because all sites in the PU were not ranged, SNAPPING causes the DERIVED_RANGE not to have the BUFGCE.

In UltraScale devices, the IO/XIPHY tile is the full height of the clock region and includes BITSLICE_CONTROL BITSLICE_RX_TX BITSLICE_TX BUFGCE BUFGCE_DIV BUFGCTRL IOB MMCME3_ADV PLLE3_ADV PLL_SELECT_SITE RIU_OR, etc.

You will need to own all of these, plus the CLB column that shares an INT tile to make the entire IOB PU.

To correctly select all if the resource in an IOB PU, please refer to (Xilinx Answer 64164).

Linked Answer Records

Associated Answer Records

AR# 64176
Date Created 04/06/2015
Last Updated 06/09/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite