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AR# 64188

UltraScale/UltraScale+ Memory IP - sys_rst missing set_false_path constraint

Description

Version Found: MIG UltraScale v7.0

Version Resolved: See (Xilinx Answer 58435)

An earlier version of (PG150) stated that the sys_rst is an asynchronous input that must be asserted for a minimum of 20 cycles of the controller clock.

Please disregard the 20 clock cycle requirement.

The sys_rst input port is an asynchronous reset which goes through synchronization logic so the 20 cycle requirement is not required and will be removed from (PG150) in a future release.

The asynchronous sys_rst port drives the PRE input pins to the MIG IP core synchronization logic but there are no set_false_path timing constraints on this path.

In some designs, this can make timing closure difficult so a set_false_path constraint should be applied to the sys_rst.

Solution

To ignore the timing paths for the asynchronous sys_rst to the synchronization logic, the following example constraint can be applied:

set_false_path -to [get_pins -hierarchical -filter {NAME =~ *infrastructure/rst*_sync_r*/PRE}]

Revision History:

04/08/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 64188
Date 01/02/2018
Status Active
Type Known Issues
Devices
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • Virtex UltraScale+
Tools
  • Vivado Design Suite
  • Vivado Design Suite - 2015.3
IP
  • MIG UltraScale
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