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AR# 64199

Vivado 2014.4 - DRC warning is reported on Bank 0 when XADC VP/VN pins are used and the Configuration bank voltage is set to 2.5V or 3.3V


When I put the following constraints in my .xdc:

set_property CFGBVS VCCO [current_design]

set_property CONFIG_VOLTAGE 3.3 [current_design]

set_property CONFIG_MODE {S_SERIAL} [current_design]

I receive the following warning if VP and VN are used:

WARNING: [Drc 23-20] Rule violation (CFGBVS-7) CONFIG_VOLTAGE with Config Bank VCCO - The CONFIG_MODE property of current_design specifies a configuration mode (BPI16) that uses pins in bank 0.  I/O standards used in this bank have a voltage requirement of 1.79999995.  However, the CONFIG_VOLTAGE for current_design is set to 2.5.  Ensure that your configuration voltage is compatible with the I/O standards in banks used by your configuration mode.  Refer to device configuration user guide for more information.


This problem is fixed in Vivado 2015.1.

XADC pins are now correctly skipped by this DRC check.

In prior releases, the warning can be ignored.

AR# 64199
Date Created 04/09/2015
Last Updated 04/22/2015
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7