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AR# 64216

High Speed SelectIO Wizard - Known Issue list

Description

This Answer Record covers the known issues with the High Speed SelectIO Wizard (v2.0) for the UltraScale family.

Note: the list of unsupported features is detailed in (PG188) LogiCORE IP High Speed SelectIO Wizard Product Guide.

As an additional reminder, the High Speed SelectIO Wizard only supports a single, positive edge clock.

Solution

In Vivado 2015.3, the High Speed SelectIO (v2.0) was introduced. It addresses a number of issues including a new reset sequence, and should be used for Native Mode designs.

Here is a breakdown of the supported mode for v2.0 and v2.1 of the High Speed SelectIO wizard:



RX Clocking
Serialization Factor
(Data Width)

HSSIO v2.0
Vivado 2015.3
RX OnlyClock used as strobe
(Edge, Center Aligned)
x4, x8Yes
1 Strobe
(Edge, Center Aligned)
x4, x8Yes
2 Strobe
(Edge, Center Aligned)
x4, x8Customization
Required
Serial mode
(Async/None/Fractional)
x4, x8Beta
TX OnlyNot applicablex4, x8Yes
RX TX1 Strobe
(Edge, Center Aligned)
x4, x8Beta
2 Strobe
(Edge, Center Aligned)
x4, x8Beta
Serial mode
(Async/None/Fractional)
x4, x8Beta

 

Beta - Currently not supported.

A full listing of answer records for the High Speed SelectIO Wizard is listed at the end of this answer record, covering all of the answer records for the High Speed SelectIO Wizard (v2.0) as well as High Speed SelectIO Wizard (v1.1) and older. v2.0 is the version of the High Speed SelectIO wizard that is available in Vivado 2015.3 and 2015.4.

For a list of current issues related to the Component Mode interface in UltraScale devices please see (Xilinx Answer 66012).

Because the High Speed SelectIO Wizard supports a range of settings, the answer records should be reviewed to determine if they are needed for a given interface.
For the High Speed SelectIO Wizard (v2.0), the following descriptions explain which answer records should be evaluated for receive interface or transmit interfaces. For Bidirectional interfaces. you should evaluate all of the answer records associated with v2.0.

Note: All RX interfaces should have the RX CLK idle until the RX VTC_RDY signal has asserted. For more information see (Xilinx Answer 66244)

For customers with multiple interfaces in a single bank, the reset MUST be applied to all interfaces at the same time to ensure that the reset sequence completes. For more information see (Xilinx Answer 66676).

Receiver Cores (RX or BIDIR)

  • To improve the performance of the PLL, the PLL should use internal compensation. See (Xilinx Answer 66159).
  • The reset state machine has been updated in 2015.3 to use the RIU clock to control the reset sequence. As a result, the RIU clock must be a continuously run clock and cannot be driven by one of the output clocks from the PLLs. To remove this restriction and use PLL output clocks to drive the RIU clock, see (Xilinx Answer 66017).
  • To Ensure that BitSlice[0] is aligned within a nibble see (Xilinx Answer 66434).
  • Ensure EN_VTCs for the BITSLICE_CONTROL are disabled until all DLY_RDY signals are asserted. See (Xilinx Answer 65988).
  • When using the High Speed SelectIO Wizard, the receive channels are set up to read each Bitslice individually and might not line up across the entire interface. To align the receive channels, see  (Xilinx Answer 66142), (Xilinx Answer 65990), (Xilinx Answer 66101), (Xilinx Answer 66431) and (Xilinx Answer 66433)
  • Additionally the example design does not check for alignment between the receive channels. To change the core to check for alignment between all of the Bitslice data, see (Xilinx Answer 66208).
  • Another restriction is that all Clocks are rising edge aligned for the generated designs. If a falling edge clock is required use (Xilinx Answer 65990) to adjust INV_RXCLK for the BITSLICE_CONTROL.
  • Because the native mode primitives such as the RX_BITSLICE, TX_BITSLICE, and BITSLICE_CONTROL are connected to specific structures, the representation of the individual bits in the Pin Selection Tab of the High Speed SelectIO Wizard does not represent the FPGA structures. See (Xilinx Answer 66100)
  • Unable to select SLVS as an IOSTANDARD. See (Xilinx Answer 67491).
.
Transmitter Cores (TX or BIDIR)

  • To improve the performance of the PLL, the PLL should use internal compensation. See (Xilinx Answer 66159).
  • To Ensure that BitSlice[0] is aligned within a nibble see (Xilinx Answer 66434).
  • To ensure the alignment of the output channels, see (Xilinx Answer 65987) and (Xilinx Answer 65988), (Xilinx Answer 66101), (Xilinx Answer 66431) and (Xilinx Answer 66433).    
  • For applications where the output channels must come up either as High or Low, the INIT attribute for the TX_BITSLICE is not controlled by the High Speed SelectIO Wizard design. To control the INIT property see (Xilinx Answer 66210).
  • Another restriction is that all clocks are rising edge aligned for the generated designs. If a negative edge clock is required use (Xilinx Answer 65990) to adjust INV_RXCLK for the BITSLICE_CONTROL.
  • Because the native mode primitives such as the RX_BITSLICE, TX_BITSLICE, and BITSLICE_CONTROL are connected to specific structures, the representation of the individual bits in the Pin Selection Tab of the High Speed SelectIO Wizard does not represent the FPGA structures. See (Xilinx Answer 66100).

Below is a full list of all known issues with the High Speed SelectIO Wizard:

Answer Record NumberInterface Type AffectedTitle Version FoundVersion Fixed
(Xilinx Answer 68163)RX & TX High Speed SelectIO Wizard - Logic might reset while waiting for DLY_RDY or VTC_RDY during the reset sequence2016.22016.3
(Xilinx Answer 68164)RX & TXHigh Speed SelectIO Wizard - Resets When Controlling en_vtc_bsc<7:0> can restart the reset sequence2016.22016.3
(Xilinx Answer 65987)TXHigh Speed SelectIO Wizard - TX - TX_GATING attribute incorrectly set.2015.3
2016.1
(Xilinx Answer 65988)Rx & TX
High Speed SelectIO Wizard - TX_RX - Bitslice Control EN_VTC asserted incorrectly 2015.32016.1
(Xilinx Answer 65990)RXHigh Speed SelectIO Wizard - RX - DATA clock defaults to non-invert (INV_RXCLK = FALSE)2015.32016.1
(Xilinx Answer 66017)RX & TXHigh Speed SelectIO Wizard - TX_RX - When using the RIU Clock the interface can fail to come out of reset.2015.32016.1
(Xilinx Answer 66101)
RX & TX
High Speed SelectIO Wizard - DELAY_TYPE or DELAY_VALUE settings may not be correctly reflected in the code2015.32016.1
(Xilinx Answer 66100)
RX & TXHigh Speed SelectIO Wizard - Bank ordering is reversed compared to the actual bank implementation from the user guide.2015.32016.1
(Xilinx Answer 66142)RXHigh Speed SelectIO Wizard - RX - For interfaces with multiple aligned channels the FIFO_RD_EN is not correctly set-up2015.32016.1
(Xilinx Answer 66159)RX & TXHigh Speed SelectIO Wizard - PLL feedback path incorrectly goes through a BUFG2015.32016.1
(Xilinx Answer 66208)RX & TXHigh Speed SelectIO Wizard - Example design does not check for alignment across the whole interface 2015.32016.1
(Xilinx Answer 66210)TX
High Speed SelectIO Wizard - The INIT value is incorrectly set for TX or RXTX designs when the default value is required to be High2015.32016.1
(Xilinx Answer 66431)RX & TXHigh Speed SelectIO Wizard - DELAY_TYPE (FIXED|VARIABLE|VAR_LOAD) is not correctly set within the synthesized netlist 2015.32016.1
(Xilinx Answer 66433)RX & TXHigh Speed SelectIO Wizard - DELAY_VALUE May not be set correctly 2015.32016.1
(Xilinx Answer 66434)TXHigh Speed SelectIO Wizard - Transmit interfaces may have TX_BITSLICE[0] out of alignment within each nibble 2015.32016.1
(Xilinx Answer 66244)RXUltraScale - Source Synchronous interfaces - RX - Requirement to have the RX CLK stopped until the RX VTC_RDY  is assertedALLALL
(Xilinx Answer 66676)RX & TXHigh Speed SelectIO Wizard - Reset requirement for 2 interfaces in one bank ALLALL
(Xilinx Answer 64217)High Speed SelectIO Wizard - Reset not following recommended sequence 2014.22015.3
(Xilinx Answer 64218)High Speed SelectIO Wizard - Unable to select Tristate function for TX Interface 2014.22015.3
(Xilinx Answer 64219)High Speed SelectIO Wizard - Maximum number of IOs that can be selected is 46 instead of 52 2014.22015.3
(Xilinx Answer 64221)High Speed SelectIO Wizard - Data width range not updating currently when sharing a bank between 2 interfaces 2014.22015.3
(Xilinx Answer 64222)High Speed SelectIO Wizard - Example design fails to implement if targeting a half bank 2014.22015.3
(Xilinx Answer 64234)High Speed SelectIO Wizard - Unable to select strobe/capture clock IO Location when switching to the RX TX Bidirectional interface type 2014.22015.3
(Xilinx Answer 64235)High Speed SelectIO Wizard : Switching between Bus Directions produces error "update of parameter PARAM_VALUE IFO.STROBEO failed2015.12015.3
(Xilinx Answer 64236)High Speed SelectIO Wizard - RXTX Bi-directional with Strobes has issue with if0_clk not having a LOC causing implementation errors 2015.12015.3
(Xilinx Answer 64291)High Speed SelectIO Wizard - Inability to select the Delay Format in the GUI

 

2014.22015.3
(Xilinx Answer 64292)High Speed SelectIO Wizard - Does not allow user to select GC_QBC for the PLL CLK source

 

2014.22015.3
(Xilinx Answer 64293)High Speed SelectIO Wizard - If using a Serialization Factor of 4 the Interface Data Speed is limited to 800Mbps 2014.22015.3
(Xilinx Answer 64282)High Speed SelectIO Wizard how to configure all 24Pairs as differential Data Pins2014.22015.3
(Xilinx Answer 64396)High Speed SelectIO Wizard - Certain frequency and data rate combinations can result in in an ERROR alert2014.22015.3
(Xilinx Answer 64503)High Speed SelectIO Wizard - Unable to select all GC pins on TX interface 2014.22015.3

** TBD = To Be Decided

Linked Answer Records

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
64217 High Speed SelectIO Wizard - Reset not following recommended sequence N/A N/A
64218 High Speed SelectIO Wizard - Unable to select 3-state function for TX Interface N/A N/A
64219 High Speed SelectIO Wizard - Maximum number of I/Os that can be selected is 46 instead of 52 N/A N/A
64221 High Speed SelectIO Wizard - Data width range not updating currently when sharing a bank between 2 interfaces N/A N/A
64222 High Speed SelectIO Wizard - Example design fails to implement if targeting a half bank N/A N/A
64234 High Speed SelectIO Wizard - Unable to select strobe/capture clock I/O Location when switching to the RX TX Bidirectional interface type N/A N/A
64235 High Speed SelectIO Wizard : Switching between Bus Directions produces error "update of parameter PARAM_VALUE IFO.STROBEO failed” N/A N/A
64236 High Speed SelectIO Wizard - RXTX Bi-directional with Strobes has issue with if0_clk not having a LOC causing implementation errors N/A N/A
64291 High Speed SelectIO Wizard - Inability to select the Delay Format in the GUI N/A N/A
64292 High Speed SelectIO Wizard - Does not allow user to select GC_QBC for the PLL CLK source N/A N/A
64293 High Speed SelectIO Wizard - If using a Serialization Factor of 4, the Interface Data Speed is limited to 800Mbps N/A N/A
64282 High Speed SelectIO Wizard how to configure all 24Pairs as differential Data Pins N/A N/A
64503 High Speed SelectIO Wizard - Unable to select all GC pins on TX interface N/A N/A
66159 High Speed SelectIO Wizard - PLL compensation mode incorrectly set N/A N/A
66208 High Speed SelectIO Wizard - Example design does not check for alignment across the whole interface N/A N/A
66017 High Speed SelectIO Wizard - TX_RX - When using the RIU Clock the interface can fail to come out of reset. N/A N/A
66101 High Speed SelectIO Wizard - DELAY_TYPE or DELAY_VALUE settings might not be correctly reflected in the code N/A N/A
66210 High Speed SelectIO Wizard - The INIT value is incorrectly set for TX or RXTX designs when the default value is required to be High N/A N/A
66100 High Speed SelectIO Wizard - Bank ordering is reversed compared to the actual bank implementation from the user guide. N/A N/A
65987 High Speed SelectIO Wizard - TX - TX_GATING attribute incorrectly set. N/A N/A
65988 High Speed SelectIO Wizard - TX_RX - Bitslice Control EN_VTC asserted incorrectly N/A N/A
65990 High Speed SelectIO Wizard - RX - DATA clock defaults to non-invert (INV_RXCLK = FALSE) N/A N/A
66431 High Speed SelectIO Wizard - DELAY_TYPE (FIXED|VARIABLE|VAR_LOAD) is not correctly set within the synthesized netlist N/A N/A
66433 High Speed SelectIO Wizard - DELAY_VALUE might not be set correctly N/A N/A
66434 High Speed SelectIO Wizard - Transmit interfaces may have TX_BITSLICE[0] out of alignment within each nibble N/A N/A
66244 UltraScale - Source Synchronous interfaces - RX - Requirement to have the RX CLK stopped until the RX VTC_RDY is asserted N/A N/A
66142 High Speed SelectIO Wizard - RX - For interfaces with multiple aligned channels the FIFO_RD_EN is not correctly set up N/A N/A
66676 High Speed SelectIO Wizard - Reset requirement for 2 or more interfaces in one bank N/A N/A
67105 High Speed SelectIO Wizard - ERROR: [Place 30-693] Unroutable Placement! PLL / BITSLICE_CONTROL component pairs are not placed in a routable site pairs. N/A N/A
67106 High Speed SelectIO Wizard - Simulation fails when using IES simulator N/A N/A
67246 UltraScale - How can large IODELAY adjustments be made using CNTVALUEIN? N/A N/A
AR# 64216
Date Created 04/10/2015
Last Updated 11/09/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale