The recommended reset Sequence for the native mode is documented in (Xilinx Answer 64198)
However the High Speed SelectIO Wizard does not adhere to these recommendations, and this can result in channel misalignment.
This issue is resolved in version 3.0 of the High Speed SelectIO Wizard, included in the 2016.1 release.
To work around this issue in older versions you can use the High Speed SelectIO Wizard to set up everything else that is required for your interface and generate the output products.
Then replace the .xci file with the <<component name>>.v and other required files.
The LOC and IOSTANDARD constraints will also need to be added.
They can be found in the <<component name>>.xdc file.
Note: the port names might need to be changed.
Once the files have been replaced you can edit the files to change the reset to follow the recommended reset sequence.
Currently the Wizard uses the inverter Locked of the PLL to reset the Bitslice delays, the Bitslices and Bitslice_Control.
Also the CLKPHYOUT_EN is tied high.
Please refer to (Xilinx Answer 64216) High Speed SelectIO - Known Issue List for software version that the issue is resolved in.