If I use the High Speed SelectIO Wizard to create a TX interface on a half bank that uses clock forwarding, the XCI can implement without any issues.
However if I use the example design, the example design creates an RX to loopback from the TX and tries to place this in the same half bank.
This results in implementation errors due to the lack of clock inputs in the half bank.
This is only an issue with the example design.
If you require the Example design to run, you can change the location for the RX portion of the example design to a different bank from the TX in the half bank.
Please refer to (Xilinx Answer 64216) High Speed SelectIO - Known Issue List for the software version that the issue is resolved in.