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AR# 64224

1G/2.5G Ethernet PCS/PMA or SGMII v15.0 - Timing failure on RST pin on IDELAYCTRL

Description

Timing failure is seen on the path to reset pin of idelayctrl with 1G/2.5G Ethernet PCS/PMA or SGMII v15.0.

Solution

To resolve the issue, please provide a reset sequence (See (Xilinx Answer 64198)) and add the following constraint to mark the failing timing path on the reset pin of IDELAYCTRL as a false path:

set_false_path -to [get_pins -hier -filter {name =~ * core_idelayctrl_i/dlyctr*/RST}]

This issue will be resolved in the 2015.3 release.

AR# 64224
Date Created 04/10/2015
Last Updated 09/16/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite - 2015.1
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII