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AR# 64236

High Speed SelectIO Wizard - RXTX Bi-directional with Strobes has issue with if0_clk not having a LOC causing implementation errors


When using the High Speed SelectIO Wizard to generate an RXTX bidirectional interface, the Wizard fails to create a LOC constraint when the CLK Scheme is set to BUFG PLL or IBUF MMCM PLL.


Currently in the High Speed SelectIO Wizard, an external clock coming in on the GC/QBC pins is used as the system clock for bi-directional interfaces.

This is used as the External Capture clock and it also drives the PLL.

Therefore only the IBUFG_PLL should be used as the CLK Scheme. 

Please refer to (Xilinx Answer 64216) High Speed SelectIO - Known Issue List for the software version that the issue is resolved in.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64216 High Speed SelectIO Wizard - Known Issue list N/A N/A
AR# 64236
Date Created 04/13/2015
Last Updated 05/14/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale