UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64249

KCU105 - UG917 (v1.1), Table 1-17 "FPGA U1 to CP2105GM U34 Connections" is incorrect

Description

The first two lines of Table 1-17 in (UG917) are incorrect. 

The function / direction and associated pins do not match up with the board schematic (U34), board constraints and Fig 1-21 in (UG917).
 
It should read:
 
G25  RX  Input  LVCMOS18  USB_UART_TX  21  TXD  Output
K26  TX  Output LVCMOS18  USB_UART_RX  20  RXD  Input

Solution

The Schematic Net Names USB_UART_TX and USB_UART_RX are named from the perspective of the CP2105GM chip, and are thus opposites from the perspective of the FPGA UART peripheral.
 
The first two lines of Table 1-17 in (UG917) (v1.1 4-Apr-2015) are incorrect.

Table 1-17 in UG917 v1.2 has been updated as follows: 
 
 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
63175 Kintex UltraScale FPGA KCU105 Evaluation Kit - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 64249
Date Created 04/14/2015
Last Updated 06/11/2015
Status Active
Type Documentation Changes
Devices
  • Kintex UltraScale
Boards & Kits
  • Kintex UltraScale FPGA KCU105 Evaluation Kit