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AR# 64251

7 Series Transceivers Wizard - In a multi-lane QPLL case, when a lane other than master lane tries to reset, the [Tx/Rx]_startup_FSM can get stuck

Description

In a multi-lane QPLL design (QPLL is shared across GTs in a QUAD), if lane 2 tries to assert reset, the FSM of lane 2 gets stuck in the ASSERT_ALL_RESETS state as the QPLLRESET from lane 2 is not connected.

Solution

To work around this issue, bypass the logic for QPLLRESET from the slave lane.

 

Steps to bypass the logic:

 

1) Add a new parameter MASTER to the <component_name>_tx_startup_fsm module:

Parameter MASTER = TRUE     // make it FALSE if it is not master

 

2) Update  the following in the <component_name>_tx_startup_fsm module: 

 

From:

    if ((TX_QPLL_USED == "TRUE" && qplllock_sync == 1'b0 && pll_reset_asserted ) ||
(TX_QPLL_USED == "FALSE" && cplllock_sync == 1'b0 && pll_reset_asserted ))
 
       tx_state  <= `DLY  WAIT_FOR_PLL_LOCK;
 

To:

    if ((MASTER == TRUE)  && ((TX_QPLL_USED == "TRUE" && qplllock_sync == 1'b0 && pll_reset_asserted ) ||
(TX_QPLL_USED == "FALSE" && cplllock_sync == 1'b0 && pll_reset_asserted )) )
 
       tx_state  <= `DLY  WAIT_FOR_PLL_LOCK;
    else if (MASTER == FALSE)  
tx_state  <= `DLY  WAIT_FOR_PLL_LOCK;
 

3) Add the parameter MASTER to the <component_name>_tx_startup_fsm module declaration in the <component_name>_init file.

For master lane i.e. lane0:

.MASTER(TRUE)

For slave lane:

.MASTER(FALSE)

 

4) Add the new parameter MASTER to the <component_name>_rx_startup_fsm module:

Parameter MASTER = TRUE     // make it FALSE if it is not master
 
5) Update the following in the <component_name>_rx_startup_fsm module:
 

From:

     if ((RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "FALSE"   && qplllock_sync == 1'b0 && pll_reset_asserted) ||
  (RX_QPLL_USED == "FALSE"&& TX_QPLL_USED == "TRUE"    && cplllock_sync == 1'b0 && pll_reset_asserted) ||
  (RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "TRUE"   ) ||
  (RX_QPLL_USED == "FALSE"&& TX_QPLL_USED == "FALSE"  )
 )
       begin
       rx_state  <= `DLY  WAIT_FOR_PLL_LOCK;
      reset_time_out <= `DLY 1b1;
    end

To:

    if ((MASTER == TRUE)  && ((RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "FALSE"   && qplllock_sync == 1'b0 && pll_reset_asserted) ||
  (RX_QPLL_USED == "FALSE"&& TX_QPLL_USED == "TRUE"    && cplllock_sync == 1'b0 && pll_reset_asserted) ||
  (RX_QPLL_USED == "TRUE" && TX_QPLL_USED == "TRUE"   ) ||
  (RX_QPLL_USED == "FALSE"&& TX_QPLL_USED == "FALSE"  )
 ) )
      begin
       rx_state  <= `DLY  WAIT_FOR_PLL_LOCK;
reset_time_out <= `DLY 1b1;
    end
    else if (MASTER == FALSE)  
      begin
       rx_state  <= `DLY  WAIT_FOR_PLL_LOCK;
reset_time_out <= `DLY 1b1;
    end
 

6) Add the parameter MASTER to the <component_name>_rx_startup_fsm module declaration in <component_name>_init file.

For the master lane i.e. lane0:

.MASTER(TRUE)

For the slave lane:

.MASTER(FALSE)

 
Revision History:
07/23/2015 - Initial Release
AR# 64251
Date Created 04/14/2015
Last Updated 07/23/2015
Status Active
Type General Article
Devices
  • Kintex-7
  • Virtex-7
  • Artix-7
IP
  • 7 Series FPGAs Transceivers Wizard