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AR# 64257

Embedded - Boot and Configuration

Description

This answer record helps you find all Embedded solutions related to boot and configuration known issues.

Solution

The Configuration Solution Center is available to address all questions related to FPGAs Configuration (not specific to Embedded Designs).


(Xilinx Answer 34904) Xilinx Configuration Solution Center

Find all you need to know about booting a Zynq-7000 device here:

(Xilinx Answer 52538) Zynq-7000 AP SoC - Boot and Configuration

Below is a list of non-Zynq topics covered by Embedded Boot and Configuration

SREC Bootloader

(Xilinx Answer 64238) SDK - 2015.1 - SREC bootloader is failing to boot image from AXI QSPI on Artix
(Xilinx Answer 63605) 2015.1 SDK: How to Create an MCS Boot Image using SPI SREC BootLoader
(Xilinx Answer 47909) 14.1 EDK - How do I boot an application from flash with the KC705?
(Xilinx Answer 50209) 14.1 EDK - How do you bootload an application from Platform Flash XL on the ML605?
(Xilinx Answer 47911) 14.1 EDK - How to bootload an application into Block RAM.
(Xilinx Answer 50257) 14.1 EDK - FlashWriter "Convert ELF to bootable SREC format" is grayed out

AXI QSPI

(Xilinx Answer 61384) 2014.2 AXI QSPI - Mismatch between RTL behavior and documentation of the Read transaction of the AXI QSPI
(Xilinx Answer 54408) IP Release Notes and Known Issues for LogiCORE IP AXI Quad SPI for Vivado 2013.4 and older tool versions

AXI EMC

(Xilinx Answer 54429) LogiCORE IP AXI External Memory Controller (EMC) - Release Notes and Known Issues for Vivado 2013.4 and older tool versions
(Xilinx Answer 59761) 2013.4 AXI External Memory Controller (AXI EMC) - Memory configurations limited relative to EDK XPS version
(Xilinx Answer 58320) Vivado 2013.3 - AXI EMC 2.0 results in "ERROR: [IP_Flow 19-3460] Validation failed on parameter 'Base Address(C_S_AXI_MEM0_BASEADDR)' for Address overlapping among various memory banks..."
(Xilinx Answer 59453) Vivado 2013.3 - Axi_EMC - Extra repetitive writes and reads happening to same address at the memory interface

HWICAP

(Xilinx Answer 58291) 2013.3 - The AXI Quad SPI forces STARTUPE2 instantiation which causes a problem with AXI HWICAP
(Xilinx Answer 45400) Spartan-6 - AXI_HWICAP locks up if I attempt to access it immediately after configuration
(Xilinx Answer 44579) 13.2 EDK, AXI_HWICAP Abort status is not captured and stored correctly
(Xilinx Answer 44578) 13.2 EDK, AXI_HWICAP - Data Read from AXI HWICAP Occurs One Clock Cycle too Early during Simulation
(Xilinx Answer 39706) 12.3 XPS_HWICAP - How do I read the WBSTAR register from the ICAP
(Xilinx Answer 59487) PetaLinux: How do I use the HWICAP driver

FLASHWRITER (non-Zynq)

(Xilinx Answer 61314) 2014.2 SDK Flashwriter - ERROR: Unable to compile flashwriter application.
(Xilinx Answer 50257) 14.1 EDK - FlashWriter "Convert ELF to bootable SREC format" is greyed out
(Xilinx Answer 59017) 14.7, 2013.4 SDK XMD - How to add debug capability to the SDK flashwriter tool

Other useful documentation

  • (PG153) LogiCORE IP AXI Quad Serial Peripheral Interface (SPI) PG100 LogiCORE IP AXI External Memory Controller (EMC)
  • (PG134) LogiCORE IP AXI HWICAP XAPP1234 Throughput Performance Measurements for AXI Quad SPI IP Core (UltraScale)
  • XAPP797 Throughput Performance Measurements for AXI Quad SPI IP Core (7 series)
  • XAPP1176 Using Execute-in-Place (XIP) with AXI Quad SPI in Vivado IP Integrator
  • XAPP1188 FPGA Configuration from SPI Flash Memory using a Microprocessor
AR# 64257
Date Created 04/14/2015
Last Updated 06/09/2015
Status Active
Type General Article
Devices
  • FPGA Device Families