In Zynq-7000, the ddrc.CHE_CORR_ECC_ADDR_REG_OFFSET and ddrc.CHE_UNCORR_ECC_ADDR_REG_OFFSET registers report row, bank, and address offset of the correctable and uncorrectable data received from DRAM device.
When ECC is enabled, ddrc.CHE_CORR_ECC_ADDR_REG_OFFSET [CORR_ECC_LOG_COL] and ddrc.CHE_UNCORR_ECC_ADDR_REG_OFFSET[UNCORR_ECC_LOG_COL] fields might not update the column address properly depending on the position of the erroneous bit in the received data word.
For example, the following sequence results into column address not being reported properly by the controller:
Note that in the above scenario, DRAM locations at each of the above addresses has single bit ECC error.
|Work-around:||None. The column address cannot be recovered, only the row and bank addresses are correct.|
|Configurations Affected:||Systems that use DDR memory and are using ECC.|
|Device Revision(s) Affected:||Refer to (Xilinx Answer 47916) Zynq-7000 Design Advisory Master Answer Record.|