UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64282

High Speed SelectIO Wizard how to configure all 24Pairs as differential Data Pins

Description

The High Speed SelectIO Wizard allows users to select a maximum of 23 differential pairs for data and one for the clock input.

Is there a way to use all of the 24 pairs in the BANK as Data pins?

Solution

The Wizard should allow 24 differential pairs when the CLK Source is PLL and the CLK Scheme is not IBUF PLL.

Currently the wizard does not have an option to do this.

To work around this issue you can use the High Speed SelectIO to set up everything else that is required for your interface and generate the output products. 

Then replace the .XCI file with the <<component name>>.v and other required files.


Please refer to (Xilinx Answer 64216) High Speed SelectIO - Known Issue List for the software version that the issue is resolved in.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64216 High Speed SelectIO Wizard - Known Issue list N/A N/A
AR# 64282
Date Created 04/15/2015
Last Updated 05/14/2015
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale
Tools
  • Vivado Design Suite