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AR# 64292

High Speed SelectIO Wizard - Does not allow user to select GC_QBC for the PLL CLK source


When using the High Speed SelectIO Wizard, I cannot select the GC_QDC pins in a bank as the clock input.

These pins are missing from the drop down menu.


If you require a different GC_QDC as the Clock input pins, do the following.

First, use the High Speed SelectIO to set up everything else that is required for your interface and generate the output products. 

Then replace the .xci file with the <<component name>>.v and other required files. 

The constraints will also need to be added.

They can be found in the <<component name>>.xdc file.

Note: the port names might need to be changed.

Change the Clock pin LOC constraint to the GC_QDC location. 

The connections between the BITSLICE_CONTROL and the BITSLICE_0 also need to be changed.

For further assistance on working around this issue, please open a Technical Support case:


Please refer to (Xilinx Answer 64216) High Speed SelectIO - Known Issue List for the software version that the issue is resolved in.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
64216 High Speed SelectIO Wizard - Known Issue list N/A N/A
AR# 64292
Date Created 04/16/2015
Last Updated 05/14/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale