I intend to create a Reconfigurable Partition (RP) pblock, which is crossing the BUFGCTRL column (center clock column) and it causes back-to-back violation.
My goal is to maximize the routability across the center of the device.
I have tried enabling and disabling the SNAPPING_MODE attribute.
When I enable SNAPPING_MODE, both interconnect columns are excluded from the RP pblock routing.
This causes routing congestion for the RP.
When I disable SNAPPING_MODE, the Interconnect column close to RP can be included into the RP pblock and the BUFGCTRL sites are no longer prohibited.
Can I allow violations around the center clock column and get SNAPPING_MODE to resolve other violations?
From Vivado 2015.1 on, a new value called "ROUTING" is added for SNAPPING_MODE to only allow violations around the center clock column.