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AR# 64300

2014.4.1 - Vivado Partial Reconfiguration - SNAPPING_MODE ROUTING for 7 series allows violations around the center clock column


I intend to create a Reconfigurable Partition (RP) pblock, which is crossing the BUFGCTRL column (center clock column) and it causes back-to-back violation.

My goal is to maximize the routability across the center of the device.

I have tried enabling and disabling the SNAPPING_MODE attribute.

When I enable SNAPPING_MODE, both interconnect columns are excluded from the RP pblock routing.

This causes routing congestion for the RP.


When I disable SNAPPING_MODE, the Interconnect column close to RP can be included into the RP pblock and the BUFGCTRL sites are no longer prohibited.


Can I allow violations around the center clock column and get SNAPPING_MODE to resolve other violations?


From Vivado 2015.1 on, a new value called "ROUTING" is added for SNAPPING_MODE to only allow violations around the center clock column.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
59964 Vivado Hierarchical Design PR - Advanced usage of the SNAPPING_MODE property for Partial Reconfiguration N/A N/A

Associated Answer Records

AR# 64300
Date 05/28/2015
Status Archive
Type General Article
  • Vivado Design Suite
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