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AR# 64306

MIG UltraScale DDR4 - Required calibration patch to resolve potential hardware failures due to incorrect DLL Reset during SDRAM initialization sequence (all configurations) and internal nibble clocking (x4 only)


Version Found: v7.0
Version Resolved: See (Xilinx Answer 58435)

This answer record includes a MIG patch applicable to Vivado 2015.1.

The patch resolve the following two issues:

Issue 1:

During DDR4 memory initialization, a DLL Reset is performed by enabling bit A8 within MR0. 

This is incorrectly disabled in the DDR4 UltraScale IP which has been seen to cause calibration failures during DQS Gate calibration.  

This answer record includes a patch to install on top of a Vivado 2015.1 installation, to ensure that when MIG generates DDR4 IP, the MR0 properly includes the enabling of the DLL Reset.

Issue 2:

The DDR4 PHY includes a parameter to enable internal nibble clocking (versus byte clocking) which is required for x4 configurations. 

In the 2015.1 release of MIG, byte clocking is incorrectly enabled for x4 interfaces. 

This answer record includes a patch to install on top of a Vivado 2015.1 installation to ensure that MIG enables internal nibble clocking for x4 configurations.


In order to resolve these issues, you must install the attached tactical IP patch.

To install the patch, extract the contents of "AR64306_vivado_2015_1_preliminary_rev1" to the 2015.1 install directory (for example, C:\Xilinx\Vivado\2015.1\), then open Vivado 2015.1 and generate all of your MIG UltraScale IP.

: This tactical patch is only compatible with the Vivado 2015.1 and MIG UltraScale v7.0 IP.


Associated Attachments

Name File Size File Type
AR64306_vivado_2015_1_preliminary_rev1.zip 8 MB ZIP
AR# 64306
Date 05/26/2015
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale
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