Version Found: DDR4 v7.0
Version Resolved: See (Xilinx Answer 69035)
This answer record includes a MIG patch applicable to Vivado 2015.1.
The patch resolve the following two issues:
During DDR4 memory initialization, a DLL Reset is performed by enabling bit A8 within MR0.
This is incorrectly disabled in the DDR4 UltraScale IP which has been seen to cause calibration failures during DQS Gate calibration.
This answer record includes a patch to install on top of a Vivado 2015.1 installation, to ensure that when MIG generates DDR4 IP, the MR0 properly includes the enabling of the DLL Reset.
The DDR4 PHY includes a parameter to enable internal nibble clocking (versus byte clocking) which is required for x4 configurations.
In the 2015.1 release of MIG, byte clocking is incorrectly enabled for x4 interfaces.
This answer record includes a patch to install on top of a Vivado 2015.1 installation to ensure that MIG enables internal nibble clocking for x4 configurations.
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