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AR# 64309

UltraScale GTH Transceiver: TX and RX Latency Values

Description

This answer record provides the TX and RX latency values for the Kintex/Virtex UltraScale FPGA GTH Transceiver. 

Solution

 

Scroll down for tables:

 

 

 

 

 

TX:

 

 

Internal Data Width 16 20 32 40 Comments
Min Max Min Max Min Max Min Max  
TX Fabric Interface Fabric width Fabric width Fabric width Fabric width Double the * values if TX_FABINT_USRCLK_INT = 1'b1 (Default is 0). Parenthesized numbers apply when Asynchronous Gearbox (Gearbox FIFO) is used.
16 32 20 40 32 64 40 80
16* 48 20* 60 32* 96 40* 120
(33*) (99)
PCIe 128B/130B Encoder       96 - 126       0 if bypass
8B/10B encoder   20 20     40 40 0 if bypass
Synchronous Gearbox
(Legacy Gearbox)
32 - 64     64 - 128 64 - 128     64B66B - 0 if bypass. Applies also to CAUI mode.
32 - 66     64 - 130 64 - 130     64B67B - 0 if bypass. Parenthesized range is for CAUI mode.
(64 - 132) (64 - 132)
Asynchronous Gearbox
(Gearbox FIFO)
      309 - 340 309 - 340     64B66B only - 0 latency when unused. When used, TX Phase FIFO is bypassed with 0 latency. If non-default TXGBOX_FIFO_INIT_RD_ADDR (IRA) is used, add (4IRA)*66 UI to latency. CAUI numbers are expected to be close to this range (309 340).
TX Phase FIFO 40-56
(56-72)
40-56
(56-72)
50-70
(70-90)
50-70
(70-90)
80-112
(112-144)
80-112
(112-144)
100-140
(140-180)
100-140
(140-180)
Using TX FIFO. Parenthesized value applies if TXFIFO_ADDR_CFG = HIGH. (Default LOW)
16 20 20 32 (0 when using Gearbox FIFO) 32 (0 when using Gearbox FIFO) 40 40 Bypassing TX FIFO.
To TX PCS/PMA boundary 16 20 20 32 32 40 40  
To Serializer 16 20 20 32 32 40 40 Nominally 1 TX XCLK cycle.
PMA 15 15 15 15 15 15 15 Serializer.
Example 1: Total in UI -- absolute minimum for given internal data width 79 95 143 175 Fabric Interface (NxN) + TX FIFO bypass + To TX PCS/PMA boundary + To Serializer + PMA.
Example 2: Total in UI -- XAUI (8B/10B mode) with TX FIFO   145 205     275 395 Fabric Interface (min NxN, max 2NxN) + 8b10b + TX FIFO (latency variation after reset) + To TX PCS/PMA boundary + To Serializer + PMA.
Example 3: Total in UI - PCIe Gen3 (128B/130B)       239 - 269       Fabric Interface (32x32) + 128B/130B Encoder + TX FIFO bypass + To TX PCS/PMA boundary + To Serializer + PMA.

 

Note: Using TXGBOX_FIFO_LATENCY DRP Register:

Actual latency through the TX Asynchronous Gearbox exceeds the latency reported by TXGBOX_FIFO_LATENCY (DRP Attribute) by ~65 UI.

The latency reported by the attribute is in units of 1/8th UI.

So, the value read out from the attribute has to be divided by 8 before adding the offset.

 

RX:

 

Internal Data Width 16 20 32 40 Comments      
Min Max Min Max Min Max Min Max        
PMA 40.5 40.5 44.5 44.5 60.5 60.5 68.5 68.5 Deserializer.      
PMA to PCS 0 0 0 0 0 0 0 0 RX FIFO used      
8 8 10 10 16 16 20 20 RX FIFO bypass: 1/2 cycle latency.      
Internal Parallel Loopback: PCS TX to RX 16 16 20 20 32 32 40 40 For internal parallel loopback only when RX FIFO is used. Latency from To TX PCS/PMA boundary of TX Table.      
Comma Alignment 32 55 40 69 64 103 80 129 Variability covers multiple modes. Parenthesized min is for XAUI. Bracketed max is for RXSLIDE PMA mode with PCS shifter.      
[33] (60) [41] [65] (120) [81]      
16 16 20 20 32 32 40 40 No Comma Alignment.      
8B/10B decoder     20 20     40 40 0 if bypass      
PCIe Decoder and Block Alignment (128B/130B)         97-127       Decoder is synchronous, but its latency varies continuously within this range during normal operation.      
PCIe RX Elastic Buffer         320 - 416 variation due to nonzero PPM       The FIFO commonly alternates between two latencies 32 UI apart in normal operation. The remaining 64 UI of variation depends on startup conditions when the FIFO starts receiving valid data.      
PCIe Decode/ Align + Elastic Buffer combined (Combination of above 2 rows)         421 - 513 variation due to nonzero PPM       Because of a correlation in the latency variation between the Decode/Aligner and the Elastic Buffer, the total variation for the combination is smaller than the sum of the variations for each one alone.      
Elastic buffer 24+ 8xML

(ML = CLK_COR_
MIN_LAT)
40 + 8xML

(ML = CLK_COR_
MIN_LAT)
30 + 10xML 50 + 10xML 48 + 8xML 80+ 8xML 60 + 10xML 100 + 10xML 0 if bypass


See important note concerning CLK_COR_MIN_LAT following the table.
For 2 byte: 4 <= ML <= 6 (phase only)
11 <= ML <= 13 (clock correction)
**Use ML = 6 for calculation
For 4 byte : 8 <= ML <= 12 (phase only)
23 <= ML <= 27 (clock correction)
**Use ML = 12 for calculation
For 8 byte: 16 <= ML <= 24 (phase only)
**Use ML = 24 for calculation
Note: concerning CLK_COR_MIN_LAT:
The value ranges shown for CLK_COR_MIN_LAT in the table are simplified guidelines for the purpose of showing sample latency ranges in the last 3 rows of the table. Use the CLK_COR_MIN_LAT value from the wizard as ML for actual latency calculations.

Phase Only is for FAST MODE
Asynchronous Gearbox
(Gearbox FIFO)
        252 348     64B66B only - 0 latency when unused. If non-default RXGBOX_FIFO_INIT_RD_ADDR (IRA) is used, add (4IRA)*66 UI to latency. 4 is the default value for the attribute      
Synchronous Gearbox
(Legacy Gearbox)
16 - 49 16 - 49     32 - 97
(32 - 98)
32 - 97
(32 - 98)
    64B66B - 0 if bypass. Parenthesized range is for CAUI mode.      
16 - 50 16 - 50     32 - 98
(32 - 100)
32 - 98
(32 - 100)
    64B67B - 0 if bypass. Parenthesized range is for CAUI mode.      
RX fabric interface Fabric width Fabric width Fabric width Fabric width        
16 32 20 40 32 64 40 80      
16* 48 20* 60 32* 96 40* 120 Fabric interface latency. Double the * values if RX_FABINT_USRCLK_INT = 1'b1 (Default is 0). Parenthesized numbers apply when Gearbox FIFO is used.      
(33*) (99)      
  0, 16       0, 32-33     Extra latency when using gearboxes (0 or 1 RXUSRCLK cycle), due to possible need for extra pipelining to align frame within fabric word.      
Example 1: Total in UI -- absolute minimum for given internal data width 81 95 141 169 PMA (round up) + PMA to PCS (FIFO bypass) + Comma Alignment bypass + Fabric Interface (NxN)      
Example 2: Total in UI -- XAUI (highest latency mode)     235 304     449 578 PMA (round up) + PMA to PCS (zero-cycle setup) + Comma Alignment (XAUI mode) + 8B/10B + Elastic Buffer (latency variation after reset) + Fabric Interface (min NxN, max 2NxN)      
Example 3: Total in UI - PCIe Gen3         578 - 671       PMA (round up) + PMA to PCS (using Elastic Buffer) + RXSLIDE PMA mode (with Comma Alignment) + PCIe Gen3 Align/Decode + PCIe Elastic Buffer (excluding PPM variation) + Fabric Interface (32x32).      

 

Note:

1. When using the RXGBOX_FIFO_LATENCY DRP Register, actual latency through RX Asynchronous Gearbox exceeds the latency reported by RXGBOX_FIFO_LATENCY (DRP Attribute) by 32 UI.

The latency reported by the attribute is in units of 1/8 th UI.

So, the value read out from the attribute has to be divided by 8 before adding the offset.

2. When using COMMA_ALIGN_LATENCY DRP Register to determine actual latency using COMMA_ALIGN_LATENCY register, use the following procedure:

Latency = 2*Internal Data Width + DRP value from COMMA_ALIGN_LATENCY register.

AR# 64309
Date Created 04/17/2015
Last Updated 11/07/2016
Status Active
Type General Article
Devices
  • Kintex UltraScale
  • Virtex UltraScale