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AR# 64331

2014.4.1 Vivado Partial Reconfiguration - Is loadless clock from static logic supported in reconfigurable module

Description

HDPR-39 mentions that the global clock net must have at least 1 flop load inside a Reconfigurable Module (RM), is it still valid?


Example DRC error:


ERROR: [Drc 23-20] Rule violation (HDPR-39) No Clock Loads Inside Reconfigurable Cell - Reconfigurable cell 'XX' has input port 'clk_XX' driven by clock driver, but it does not have flop loads. Global clock net must have at least 1 flop load inside reconfigurable module

Solution

The following scenario should be supported:

A Reconfigurable Partition (RP) has 2 RMs: RM1 and RM2.

In RM1, only clk1 is used and clk2 is loadless.



In RM2, only clk2 is used and clk1 is loadless.


So HDPR-39 DRC is invalid, and now it is disabled for all of the devices.

In Vivado the loadless clock in the RM can be routed properly.

AR# 64331
Date Created 04/20/2015
Last Updated 05/26/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite