Vivado supports automatic clock propagation to the UltraScale GT output clock pins, so the UltraScale GT output clocks do not need to be manually constrained.
(See Q3 for more information about gigabit transceiver output clocks)
- (UG903) Using Constraints - Section "Primary Clocks" and "Virtual Clocks".
- (Xilinx Answer 59030) - The effect on timing analysis when using create_clock to define a clock on internal objects.
Q2. What is a Virtual clock?
A2. A Virtual clock is a clock that does not exist in the design and is usually used to constrain the input and output interface.
- (UG903) Using Constraints - Section "Virtual Clocks".
- (Xilinx Answer 59893) - An example where the virtual clock is used to constrain the input delay.
- (Xilinx Answer 55287) - An example where the virtual clock is used to constrain input to output feed-through paths.
Q3. How to constrain Gigabit Transceiver (GT) output clocks?
Q4. How to constrain clocks on differential ports?
Q5. Critical Warning is reported on a constraint in an IP XDC complaining that a clock object or an object related to clock cannot be found.
Why does the IP XDC not work?
A5. The clock from the user design that is used by an IP needs to be defined with create_clock or create_generated_clock in the user XDC and needs to be processed before it is used by the IP constraints.
These issues are mostly due to missing top level clock definitions or incorrect constraints ordering.
- (UG903) Using Constraints - Section "Ordering Your Constraints" and "Constraints Scoping".
- (Xilinx Answer 57056) - An example where the issue occurs due to missing clock definition or incorrect constraints order.
- (Xilinx Answer 53805) - An example where the issue occurs due to the clock definition being overridden.