Post-synthesis functional simulation is generating the following warning in reference to the sp_ram module during static elaboration:
The module is defined in a file named sp_sync_ram.vhd, which has been added under design sources and marked for use in both synthesis and simulation.
As a result, this module is treated as a black box and the output from the module shows all undefined 'U' values.
This issue is typically seen when the SOURCE_MGMT_MODE property of current_project is set to DisplayOnly. (The Sources window popup menu command "Hierarchy Update" is set to "Automatic Update, Manual Compile Order".)
For post-synthesis simulation in DisplayOnly mode, the design graph calculates all of the files from the simset and the netlist.
Automatic computation of side files from the source fileset in DisplayOnly mode is not performed. Therefore if the file is not included in a simset, it is not included in .prj and not passed to Vivado Simulator for compilation.
As a work-around, you need to add the missing files manually to the simulation fileset and set the used_in values as below:
Alternatively, users can set the "Hierarchy Update" to "Automatic Update and Compile Order", which equivalently sets SOURCE_MGMT_MODE to ALL.
Those files from the source fileset will be fetched automatically in post-synthesis or post-implementation simulation.