We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64395

2014.4 AXI Ethernet: IDELAYS Not Calibrated


I am using the AXI Ethernet Subsystem IP in my design. 

I am trying to adjust the IDELAY value on the rxd and rx_ ctl inputs, but it appears to be working incorrectly. 

Debug probes on the reset input and ready output from the IDELAYCTRL component show that the reset is static 1 and the ready is static 0, so I believe the IDELAYs are not being calibrated.

What should I do?


The reason that the reset is driven high is because there is a component called bd_ 0_ eth_ mac_ 0_ support_ resets.vhd that does an OR operation between either an external reset or a NOT of the ready output from the IDELAYCTRL (line 125) to initiate a reset to the IDELAYCTRL.

Because the IDELAYCTRL reset input is high, the ready output stays low and the reset continues to stay high.


Modify the file bd_0_eth_mac_0_support_resets.vhd at line 125 from:

idelayctrl_reset_in <= glbl_rst or not idelayctrl_ready;


idelayctrl_reset_in <= glbl_rst;

AR# 64395
Date Created 04/28/2015
Last Updated 05/28/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Kintex-7
  • Kintex-7Q
  • More
  • Artix-7
  • Artix-7Q
  • Zynq-7000
  • Zynq-7000Q
  • Virtex-7
  • Virtex-7 HT
  • Virtex-7Q
  • Less
  • Vivado Design Suite - 2014.4
  • AXI Ethernet