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AR# 64407

AXI Performance Monitor - How can I evaluate the performance of my Zynq device using the AXI Performance Monitor


This brief demo show how to capture the performance of a Zynq device using the AXI Performance monitor IP and the AXI Traffic Generator.

This demo uses the driver API for the APM in an SDK application.


This demo shows how to manually set up the performance monitor.

Step 1: Create the Hardware

This demo targets a ZC702 board.

However, any Zynq device can be used.

Launch Vivado 2015.1, and create a Block Design (BD).

Add the following IP

  • AXI Performance Monitor
  • AXI Traffic Generator x 6
  • AXI interconnect x 7
  • Constant x 6
  • Zynq Processing System
  • Processor System Reset

Highlight 1 AXI Traffic Generator, 1 AXI interconnect, and 1 Constant IP and select Create Hierarchy.

Name this "TrafficGenX"

Where X will be 0 -> 5

Repeat this for all the AXI Traffic Generators.

Click into TrafficGen0, and configure the AXI Traffic Generator as follows.

Click on Interconnect, and configure as follows:

The Concat IP, should be set to 1, and 1 for width and val.

Next, highlight the following pins and make them external:

  • interconnect/ARESETN
  • interconnect/S00_ACLK
  • interconnect/M00_AXI
  • interconnect/S00_ARESETN

Finally, make the connection below:

Close the TrafficGen0 hierarchy, and return to main BD canvas and remove the external pins:

Repeat this for all ATG hierarchies (except TrafficGen5, which has a AXI Master Width of 32 instead of 64)

Double Click on the AXI Performance Monitor IP to configure as shown below:

Run Block Automation (only applicable for demo boards).

The Zynq GUI will now appear.

Select OK.

Double Click on the Zynq Processing System, and configure the interfaces as shown below:

  • Connect TafficGen0/M00_AXI -> ZYNQ Processing System/S_AXI_HP0, and AXI Performance Monitor/SLOT_0_AXI
  • Connect TafficGen1/M00_AXI -> ZYNQ Processing System/S_AXI_HP1, and AXI Performance Monitor/SLOT_1_AXI
  • Connect TafficGen2/M00_AXI -> ZYNQ Processing System/S_AXI_HP2, and AXI Performance Monitor/SLOT_2_AXI
  • Connect TafficGen3/M00_AXI -> ZYNQ Processing System/S_AXI_HP3, and AXI Performance Monitor/SLOT_3_AXI
  • Connect TafficGen4/M00_AXI -> ZYNQ Processing System/ACP, and AXI Performance Monitor/SLOT_4_AXI
  • Connect TafficGen5/M00_AXI -> ZYNQ Processing System/S_AXI_GP0, and AXI Performance Monitor/SLOT_5_AXI
  • Connect ZYNQ Processing System/FCLK_CLK0 -> Processor System Reset/slowest_sync_clk
  • Connect ZYNQ Processing System/FCLK_RESET0_N -> Processor System Reset/ext_reset_in
  • Connect Processing System Reset/interconnect_aresetn[0:0] -> TrafficGen[0-5]/ARESETN and AXI Interconnect/ARESETN
  • Connect Processing System Reset/peripheral_aresetn[0:0] -> TrafficGen[0-5]/S00_RESETN, AXI Performance Monitor/slot_[0-5]_axi_aresetn, AXI Performance Monitor/s_axi_aresetn, AXI Performance Monitor/core_aresetn, and AXI Interconnect/S00_ARESETN/M00_AREESETN
  • Connect all clocks -> ZYNQ Processing System/FCLK_CLK0
  • Connect ZYNQ Processing System/M_AXI_GP0 -> AXI Interconnect/S00_AXI
  • Connect AXI Interconnect/M00_AXI -> AXI Performance Monitor/S_AXI

Open the Address Editor, right click on the processing_system7_0, and select Auto Assign Address.

Generate Output Products.

Generate HDL wrapper.

Generate Bitstream.

Export to SDK.

Step 2: Create Application

In SDK, create a new Empty Application.

To do this, select New -> Application Project, and follow the steps below:

Once this is done, right click on the src folder in the newly created application project, and follow the steps below:

Open the apm_test.c and copy in the source code attached to this AR.

Save and build.

Once this is done, the application is ready to test.

Note: This source code is to be used as reference only.

For more information on the API used here, please see the APM driver:

<SDK Install>\data\embeddedsw\XilinxProcessorIPLib\drivers\axipmon_v6_1\src


Associated Attachments

Name File Size File Type
apm_test.c 2 KB C
AR# 64407
Date Created 04/29/2015
Last Updated 06/19/2015
Status Active
Type General Article
  • Vivado Design Suite - 2015.1