We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64410

UltraScale/UltraScale+ Memory IP - Can either external or internal VREF be used?


The DDR4 UltraScale IP supports only internal VREF. 

The DDR3/RLDRAM3/QDRII+ UltraScale IPs support both external and internal options for VREF.

Because VREF selection is specific to I/O pin planning (which has been removed from MIG in the 2015.1 version of Vivado), the option to select external versus internal is not provided within the MIG customization tool.

Is internal or external VREF recommended? 

What is needed to properly configure the memory interface I/O to use internal or external VREF?


Internal Versus External VREF Recommendations

The UltraScale internal VREF circuit includes enhancements compared to the 7 Series internal VREF circuit.

Whereas 7 Series MIG had datarate limitations on internal VREF usage (see (Xilinx Answer 42036)), internal VREF is recommended in UltraScale.

The VREF for 7 Series had coarse steps of VREF value that were based on VCCAUX.

This saved pins but limited the performance because VCCAUX did not track with VCCO as voltage went up and down.

Not being able to track with VCCO enforced the performance limitations of internal VREF in MIG 7 Series.

UltraScale includes several changes to internal VREF including a much finer resolution of VREF for DDR4 read VREF training.

Additionally, internal VREF is based on the VCCO supply enabling it to track with VCCO.

Internal VREF is not subject to PCB and Package inductance and capacitance.

These changes in design now give internal VREF the highest performance.

Steps for configuring Internal or External VREF

Because internal VREF is required for DDR4, the UltraScale IP is automatically configured for internal VREF usage.

The VREF value listed in the below noted constraint is not used with DDR4 PODL12 I/Os.

For DDR4, the initial value is set, by default, to 0.84V.

The calibration logic, starting in MIG 7.1 released with Vivado 2015.2., then adjusts this voltage as needed for maximum interface performance.

The following steps should be followed for DDR3, RLDRAM3, and QDRII+ UltraScale IP.

1) Follow board requirements for external or internal VREF as per the (UG571) UltraScale Architecture-Based FPGAs SelectIO Resources User Guide.


2) To use internal VREF, the FPGA banks containing inputs require a constraint specifying the banks and voltage.

This can be manually added to the XDC or entered using I/O Pin Planner (see UG899 > Creating an INTERNAL_VREF Constraint).

A sample for DDR3 SSTL15 is shown here:

set_property INTERNAL_VREF 0.750 [get_iobanks 45]

A sample for RLDRAM3 SSTL12 is shown here:

set_property INTERNAL_VREF 0.600 [get_iobanks 45]

A sample for QDRII+ HSTL_I is shown here:

set_property INTERNAL_VREF 0.750 [get_iobanks 45]

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
58435 UltraScale/UltraScale+ Memory IP - Master Release Notes and Known Issues N/A N/A
AR# 64410
Date 01/17/2018
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale
  • Kintex UltraScale+
  • More
  • Virtex UltraScale+
  • Zynq UltraScale+ MPSoC
  • Less
  • Vivado Design Suite
  • MIG UltraScale
Page Bookmarked