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AR# 64458

FIFO Generator - simulation mismatch between XCI and Funcsim

Description

  1. I first perform a Verilog based behavioral simulation of a target FPGA using a standalone scripted simulation environment based on ModelSim SE 10.2b.

  2. I then compile the design for my testbench using the FIFO "*_funcsim.v" models contained within the various Vivado generated IP folders ({myproj}.srcs\sources_1\ip\fifo_xyz\fifo_xyz_funcsim.v) 

Unlike the first more rudimentary Vivado-launched ModelSim simulation, my second simulation shows that the FPGA's FIFO are missing the first dataword being written into them. 

Why is there a functional difference between the two?

The Simulation model should be identical to core behavior.

Solution

This is the known issue with the FIFO Generator core.

This issue has been fixed in the Vivado 2015.1 Release.

AR# 64458
Date Created 05/06/2015
Last Updated 08/28/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2014.4.1
IP
  • FIFO Generator