We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 6446

8.1i Timing/Constraint - OFFSET OUT/BEFORE does not use clock period during calculation


I placed an OFFSET OUT/BEFORE constraint on a path, but the values reported by Timing Analyzer/TRACE are different than when I calculated them based on the equations in (Xilinx Answer 5489). Why is this happening?


An OFFSET OUT/BEFORE constraint does not use the required clock period if the output register does not clock anything. This occurs when the register clocks a constant, and a reset is used to clear the register (also called a "one shot"). As there is no data path (with a period) associated with the register, the tools cannot find the period, and they incorrectly calculate the output offset.

One way to work around this problem is to enable path tracing for the reset -> CLK setup checking by adding the following to the PCF:


This issue will be addressed in a future software release.

AR# 6446
Date Created 08/21/2007
Last Updated 01/18/2010
Status Archive
Type General Article