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AR# 64503

High Speed SelectIO Wizard - Unable to select all GC pins on TX interface


When using the High Speed SelectIO Wizard to set up a TX interface where the CLK Scheme is set to BUFG PLL, no Clock I/O Loc constraints should be created. 

However, the Wizard does not allow me to select all of the available GC pins in the bank for data.


Even though there is no Clock I/O Loc constraint, whichever pin was selected as the Clock I/O Pin Loc before the CLK Scheme was changed to BUFG PLL gets held back by the Wizard and cannot be chosen for Data. 

This is a Known Issue with the Wizard.

The Wizard does not actually create a LOC constraint for the CLK input pins it just stops the user from selecting it for data. 

To work around the issue, if not all the GC pins are required for data you can temporarily change the Clk Scheme to IBUF PLL on the Settings Tab, then go to the Pin Assignment Tab and select the GC pin that is not required for data as your Clk location. 

Then go back to the Settings tab and change the Clk Scheme to BUFG PLL.


To work around this issue you can use the High Speed SelectIO to set up everything else that is required for your interface and generate the output products. 

Then replace the .XCI file with the <<component name>>.v and other required files. 

The constraints will also need to be added.

They can be found in the <<component name>>.xdc file.

Note: the port names may need to be changed.


You need to add a BITSLICE for the GC location required and the connections between the BITSLICE_CONTROL and this BITSLICE also need to be added.

For further assistance on working around this issue, please open a Technical Support case:


Please refer to (Xilinx Answer 64216) High Speed SelectIO - Known Issue List for the software version that the issue is resolved in.

AR# 64503
Date Created 05/08/2015
Last Updated 05/15/2015
Status Active
Type General Article
  • Kintex UltraScale
  • Virtex UltraScale