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AR# 64514

2015.1 UltraScale Partial Reconfiguration - route_design fails with missing Partpin LOC on design with pblock spanning Laguna interfaces

Description

In my Partial Reconfiguration (PR) design targeting UltraScale SSI devices, the Reconfigurable Module (RM) pblock has paired Laguna across multiple SLRs.


During route_design, I receive an error complaining about missing Partpin LOCs (PPLOC):


[Constraints 18-4430] On the boundary net XX/ramp_reg_1/R18/R0/O1, the routing branch between node INT_X34Y264/IMUX_E14 and node CLEL_R_X12Y287/CLE_CLE_L_SITE_0_GQ2 does not contain PartPin LOC. In partial reconfiguration flow, the routing branch between static logic and reconfigurable logic must have PartPin LOC.
[Constraints 18-4430] On the boundary net XX/ramp_reg_1/R18/R0/O1, the routing branch between node INT_X34Y264/IMUX_E15 and node CLEL_R_X12Y287/CLE_CLE_L_SITE_0_GQ2 does not contain PartPin LOC. In partial reconfiguration flow, the routing branch between static logic and reconfigurable logic must have PartPin LOC.
[Constraints 18-4430] On the boundary net XX/ramp_reg_1/R18/R0/O1, the routing branch between node INT_X34Y264/IMUX_W20 and node CLEL_R_X12Y287/CLE_CLE_L_SITE_0_GQ2 does not contain PartPin LOC. In partial reconfiguration flow, the routing branch between static logic and reconfigurable logic must have PartPin LOC.

How can I resolve this issue?

Solution

This routing congestion is caused by PPLOCs spreading over two SLRs.

To work around the issue, you can try to constrain all of these PPLOCs in a single SLR.

In Vivado 2015.2, all PPLOCs in the RM pblock spanning multiple SLRs are automatically placed in a single SLR by the placer to improve routing congestion.
AR# 64514
Date Created 05/10/2015
Last Updated 06/09/2015
Status Active
Type General Article
Tools
  • Vivado Design Suite - 2015.1