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AR# 64542

ERROR: [Drc 23-20] Rule violation (PLIDC-3) when instantiating the same SelectIO Wizard IP core several times


When instantiating multiple instances of the same SelectIO Wizard IP core, the following error might be displayed:

ERROR: [Drc 23-20] Rule violation (PLIDC-3) IDELAYCTRL DRC Checks - IDELAYCTRL instances '<SelectIO wizard IP hierarchical name #1>/inst/delayctrl' and '<SelectIO wizard IP hierarchical name #2>/inst/delayctrl' have same IODELAY_GROUP '<SelectIO wizard IP name>_group' but their REFCLK signals are different.

The SelectIO Wizard IP core contains IODELAY_GROUP constraints in the HDL code which is common for all instances.

(* IODELAY_GROUP = "selectio_wiz_0_group" *)

Because all instances use the same HDL code, but have different signals, this DRC error is issued.


To work around this issue you will need to edit the IODELAY_GROUP constraint in HDL and over-ride it with XDC constraints.

To edit the HDL open the <SelectIO Wizard IP name>_selectio_wiz.v file and search for the (* IODELAY_GROUP = "selectio_wiz_0_group" *) lines.

There will be one for the DELAY and another for the IDELAYCTRL. Comment out each of these lines as you are going to constrain the groups in the XDC file.

Then in the XDC file create an IODELAY_GROUP for each instance of the SelectIO Wizard.

The constraints can be kept generic, so all delay elements (IDELAYCTRL and IODELAY primitive) in an instance are constrained to the same group. 

set_property IODELAY_GROUP <SelectIO Wizard IP name>_group1 [get_cells <SelectIO wizard IP hierarchical name #1>/inst/*delay*]
set_property IODELAY_GROUP <SelectIO Wizard IP name>_group2 [get_cells <SelectIO wizard IP hierarchical name #2>/inst/*delay*]

AR# 64542
Date 07/21/2017
Status Active
Type General Article
  • Kintex-7
  • Virtex-7
  • Artix-7
  • Vivado Design Suite
  • Vivado Design Suite - 2014.4
  • Vivado Design Suite - 2014.4.1
  • Vivado Design Suite - 2015.1
  • SelectIO Wizard
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