Version Found: v7.1
Version Resolved: See (Xilinx Answer 58435)
The product guide recommends ROW_COLUMN_BANK for the ordering of the memory controller.
Due to changes in the MIG controller for UltraScale, this will cause low performance for AXI interfaces.
To improve the efficiency of the AXI interface, the parameter AUTO_AP_COL_A3 should be set to "ON" in the RTL located in the files below.
You will need to update the file which matches the memory type you have selected:
06/25/2015 - Initial Release