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AR# 64619

2015.1 Vivado IP Release Notes - All IP Change Log Information

Description

This answer record contains a comprehensive list of IP change log information from Vivado 2015.1 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

Solution

(c) Copyright 2015 Xilinx, Inc.

All rights reserved.

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100G Ethernet (1.5)

* Version 1.5

* Simplex TX/RX

* 1588 1 step Ordinary Clk

* AXI4 Lite User Interface for Duplex

* GT RX Buffer Bypass feature with Single-Lane for CAUI-4 Mode

10G Ethernet MAC (15.0)

* Version 15.0

* Product name changed from Ten-Gigabit Ethernet MAC to 10G Ethernet MAC for Ethernet naming consistency across the Vivado IP catalog

* Updated AXI4-Lite logic to correctly handle pipelined/concurrent accesses

* Significant round-trip (transmitter and receiver) latency reductions for 64-bit datapath permutations

* Added support for stacked VLAN frames (QinQ) as defined in 802.1ad

* Updated RX Length Type Error statistics counter to only increment if frame doesn't have an FCS error

* Updated 32-bit logic to ensure a type/length of 0x600 is classed as a type

* Fixed a corner case issue in the 32-bit logic where the first frame transmitted after resuming from pause could be corrupted

* Fixed example design FIFO to always recover cleanly after overflow conditions

* Example design FIFO now instantiates dedicated clock domain crossing synchronization modules to be consistent with the rest of the example design

* Example design transmitter FIFO enhanced to achieve full line rate performance under all operating conditions

10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

* Version 6.0

* Product name changed from Ten-Gigabit Ethernet PCS/PMA (10GBASE-R/KR) to 10G Ethernet PCS/PMA (10GBASE-R/KR) for Ethernet naming consistency across the Vivado IP catalog

* Switch to use the Async 64/66 Gearbox in the UltraScale transceivers for 10GBASE-KR support

* For UltraScale devices, use of the Async 64/66 Gearbox has enabled the clocking logic to be simplified in 64-bit data path permutations.  txusrclk2 is now used as the clock source for the data path logic.  Please consult the Product Guide

* For UltraScale devices, added an option to select the transceiver reference clock frequency used by the core

* Use a 64-bit interface to the UltraScale transceiver for 64-bit data path permutations

* Added an option to enable the removal of the elastic buffer for all UltraScale designs

* Some pins have been renamed, added and removed to support more features and be more agnostic with clock frequencies. Please consult the Product Guide for details

* Replaced a few remaining VHDL RTL files with Verilog to allow pure-Verilog simulations

* Added rxrecclk_out port in all configurations

* For 10GBASE-KR permutations, added the ability to submit a pending Load XNP Page Data command along with the XNP data, before enabling AutoNegotiation

* Added ability to set the DCLK frequency during core configuration. For UltraScale devices, DCLK must come from a free-running clock source

* For 7-Series devices, latency through the transmit path is increased by two cycles of txusrclk2 to a avoid potential, one-off empty indication

* Added qpll0reset output port for UltraScale devices to permutations that have shared logic in the example design.  This port is used to drive the QPLLRESET input of the GT COMMON

* Added automatic enabling of FEC during Autonegotiation, where both link partners have FEC ability and at least one has requested FEC enablement

* Now using the UltraScale GT Wizard Reset Helper Block for all cores on UltraScale devices

* Added preset values and resets for some registers, for completeness

10G Ethernet Subsystem (3.0)

* Version 3.0

* Product name changed from AXI 10G Ethernet Subsystem to 10G Ethernet Subsystem for Ethernet naming consistency across the Vivado IP catalog

* For UltraScale devices, use of the Async 64/66 Gearbox has enabled the clocking logic to be simplified.  txusrclk2 is now used as the clock source for the data path logic.  Please consult the Product Guide for details.

* For UltraScale devices, added an option to select the transceiver reference clock frequency used by the core

* Significant round-trip (transmitter and receiver) latency reductions for 64-bit datapath permutations

* Added 10GBASE-R 32-bit datapath options for the core to provide lower utilization and latency

* Added an option to enable the removal of the RX elastic buffer for all UltraScale designs, to further reduce latency and utilization

* Added IEEE1588 timestamping support to UltraScale 10GBASE-R permutations

* Added support for stacked VLAN frames (QinQ) as defined in IEEE802.1ad

* Added automatic enabling of FEC during Autonegotiation, where both link partners have FEC ability and at least one has requested FEC enablement

* Now using the UltraScale GT Wizard Reset Helper Block for all cores on UltraScale devices.  The dclk input from the core must be connected to a free-running clock source for UltraScale devices.

* Some pins have been renamed, added and removed to support more features and be more agnostic with clock frequencies. Please consult the Product Guide for details.

* Added rxrecclk_out port in all configurations

* Added qpll0reset output port for UltraScale devices to permutations that have shared logic in the example design.  This port is used to drive the QPLLRESET input of the GT COMMON

* Added customization options to set the frequency of DRP clock and AXI-Lite clock.

* 7-Series 1588 permutations: connected up the reset port of the MMCM in the shared logic to the MMCM_RESET output signal from the tx_startup_fsm module to improve reset/initialization reliability.  The dclk input from the core must be connected to a free-running clock source for 1588 permutations.

* 7-Series 1588 permutations: connected up the QPLL_RESET output port of the tx_startup_fsm module to the QPLLRESET of the GT COMMON to improve reset/initialization reliability.

* 7-Series 1588 permutations: added txfsmreset_request output port for permutations that have shared logic in the example design. This is an OR of internal core transmitter reset sources (such as a PMA reset request).  txfsmreset_request will restart the tx_startup_fsm module to trigger a full reset and buffer bypass phase alignment of the transceiver to improve reset/initialization reliability.

* Added a new self-contained shared logic wrapper within the example design for permutations where shared logic is included in the example design.  This will reduce the amount of file editing when adding the shared to customer projects.

* Fixed example design FIFO to always recover cleanly after overflow conditions.

* Example design FIFO now instantiates dedicated clock domain crossing synchronization modules to be consistent with the rest of the example design.

* Example design transmitter FIFO enhanced to achieve full line rate performance under all operating conditions

* Enhanced demonstration test bench to terminate immediately after successful frame reception when in DEMO_TB mode rather than waiting for a long fixed duration before self terminating.

1G/2.5G Ethernet PCS/PMA or SGMII (15.0)

* Version 15.0

* Added 2.5 Support for Series-7 Devices(Except Artix-7 and Zynq devices with Artix Fabric) and UltraScale Devices.

* 1588 permutations using the Time-of-Day format, An issue has been fixed in the receiver timestamp whereby the seconds field could occasionally be in advance by 1 second.

* Fixed SGMII over LVDS issue in deserialization for UltraScale Devices.

* Added options for gtrefclk and DRP/Freerun Clock (Independent Clock) in GUI for UltraScale Devices.

* Default Series-7 Equalization changed to LPM from DFE for GTHE2 and GTXE2 transceivers to match GT Wizard.

* GT wizard updated to v3_5 for Series-7 transceivers.

* Moved required BUFG on gtrefclk in devices with GTHE2 and GTXE2 to shared logic.

* Moved BUFG on recovered clock to shared logic.

* Added mmcm_reset output port for configurations using transceiver to reset the external mmcm to generate userclk/userclk2.

* Constraints updates.

* Added txinhibit to the transceiver debug signals.

* Added pcsrsvdin to the transceiver debug signals for UltraScale devices.

* C_RUDI behavior fixed by adding pipeline on RXCLKCORCNT.

* gtwizard_ultrascale upgraded to v1_5.

32-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 6)

* No changes

3GPP LTE Channel Estimator (2.0)

* Version 2.0 (Rev. 8)

* Internal GUI updates.  No functional changes.

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

* Sub-core HDL updated to resolve placement issues, no functional change

3GPP LTE MIMO Decoder (3.0)

* Version 3.0 (Rev. 8)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

3GPP LTE MIMO Encoder (4.0)

* Version 4.0 (Rev. 7)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

3GPP Mixed Mode Turbo Decoder (2.0)

* Version 2.0 (Rev. 8)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

3GPP Turbo Encoder (5.0)

* Version 5.0 (Rev. 7)

* Internal GUI updates.  No functional changes.

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

3GPPLTE Turbo Encoder (4.0)

* Version 4.0 (Rev. 7)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

64-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 6)

* No changes

7 Series FPGAs Transceivers Wizard (3.5)

* Version 3.5

* Updated the GTZ CTLE tuning code to enable tuning of individual lanes.

* Added separate resets for TX and RX startup FSMs except for GTZ.

7 Series Integrated Block for PCI Express (3.1)

* Version 3.1

* Added support for xc7a35ti,xc7a50ti,xc7a75ti,xc7a100ti and xc7a200ti devices.

* Added non-default input port pipe_txinhibit.

* Fixed issue with invalid link width and speeds for -1 speed grade for devices xc7z030i and xc7z015i devices (x8 is not supported and incase of xc7z015i only Gen1 speeds are supported when speedgrade -1 is selected).

* Added support for new packages: fbv484,fbv676,ffv1156,ffv900,fbv900 and ffv901

* Added shared logic support for RP configuration.

* Modified the External Pipe Interface as Master for Rootport configuration and Slave for Endpoint and Legacy Endpoint configurations.

* Update to generate a 100MHz icap_clk for tandem configurations rather than using the ref_clk input.

* Removed 250Mhz User clock frequency option for all -1,-1I,-1M,-1Q,-1L speedgrades of Artix7 family.

AHB-Lite to AXI Bridge (3.0)

* Version 3.0 (Rev. 3)

* AHBLite interface definition updated to v2.0

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI 1G/2.5G Ethernet Subsystem (7.0)

* Version 7.0

* Support 2.5G Data Rates over SGMII and 1000BaseX in non-processor mode.

* Support multiple GT clock frequencies for UltraScale devices.

* Moved BUFG in devices with GTPE2, GTHE2 and GTXE2 to shared logic.

* Moved BUFG on recovered clock to shared logic.

AXI AHBLite Bridge (3.0)

* Version 3.0 (Rev. 3)

* AHBLite interface definition updated to v2.0

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI APB Bridge (3.0)

* Version 3.0 (Rev. 3)

* Warning messages in IPI have been improved, no functional changes.

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI BFM Cores (5.0)

* Version 5.0 (Rev. 5)

* Repackaged to improve internal automation, no functional changes.

* Enhanced IPI support to update number of outstanding transaction on AXI interfaces

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI BRAM Controller (4.0)

* Version 4.0 (Rev. 4)

* Increased the supporting memory depth to 256k

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI Bridge for PCI Express Gen3 Subsystem (1.1)

* Version 1.1

* Added non-default ports ext_ch_gt_drp_addr, ext_ch_gt_drp_en, ext_ch_gt_drp_di, ext_ch_gt_drp_do, ext_ch_gt_drp_rdy, ext_ch_gt_drp_we and ext_ch_gt_drpclk to access the GT DRP ports for debugging purpose as per the requirement. These ports and interface are enabled using the model parameter EXT_CH_GT_DRP.

* Added Transceiver debug and status ports as a part of EOU item

* Added support for new packages: flvb1760,ffvd1517,ffvc1517,flva2104,flvd1517 and flvb2104

* Fixed issue with MRd transaction during linkdown (Xilinx Answer 63113)

* Added support for GUI option to select PLL_TYPE for Gen2 Speed: CPLL (Optional) and QPLL1 (Default)

* Added support for GUI option to select CORE_CLK_FREQ for Gen3 x1/x2/x4: 250 MHz (Default) and 500 MHz (Optional)

* Added PCIe specific production settings for VU095-ES2

* Removed support for 250 MHz user clock and axis clock for -1/-1L/-1LV speedgrades

* Removed GUI Parameter prefetch enable for BAR1, BAR3 and BAR5

AXI CAN (5.0)

* Version 5.0 (Rev. 8)

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI Central Direct Memory Access (4.1)

* Version 4.1 (Rev. 5)

* Support for up to 64 bit address

* Supported devices and production status are now determined automatically, to simplify support for future devices

* No functional changes

AXI Chip2Chip Bridge (4.2)

* Version 4.2 (Rev. 4)

* Enhanced support for 128 data width and 64 address width

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to all clock interfaces

* Example design updated to use Aurora64b66b_v10 and Aurora8b10b_v11

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI Clock Converter (2.1)

* Version 2.1 (Rev. 4)

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI Crossbar (2.1)

* Version 2.1 (Rev. 6)

* Improved automation of Mmm_Sss_(READ|WRITE)_CONNECTIVITY, Sss_(READ|WRITE)_ACCEPTANCE and Mmm_(READ|WRITE)_ISSUING parameters in IP Integrator

* Improved automation of READ_WRITE_MODE parameter of IP Interfaces in IP Integrator

* Update IP Integrator automation Tcl to accommodate changes to find_bd_objs IP integrator command.

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface CLKIF

* Improved HDL code to reduce compiler warnings.

AXI Data FIFO (2.1)

* Version 2.1 (Rev. 4)

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI Data Width Converter (2.1)

* Version 2.1 (Rev. 5)

* Improved automation of NUM_READ_OUTSTANDING and NUM_WRITE_OUTSTANDING IP Integrator Interface properties when FIFO_MODE > 0

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI DataMover (5.1)

* Version 5.1 (Rev. 6)

* Support for up to 64 bit address

* Supported devices and production status are now determined automatically, to simplify support for future devices

* No functional changes

AXI Direct Memory Access (7.1)

* Version 7.1 (Rev. 5)

* Support for up to 64 bit address

* Supported devices and production status are now determined automatically, to simplify support for future devices

* No functional changes

AXI EMC (3.0)

* Version 3.0 (Rev. 4)

* Updated IP to get Bus Width from common utilities for Board.

* Updated rtl to correctly generate ADV_LDN output.

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI EPC (2.0)

* Version 2.0 (Rev. 7)

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI Ethernet Buffer (2.0)

* Version 2.0 (Rev. 7)

* Using Global board utilities for uniformity across all IPs.

AXI Ethernet Clocking (2.0)

* Version 2.0 (Rev. 1)

* No changes

AXI EthernetLite (3.0)

* Version 3.0 (Rev. 3)

* XDC updated to fix DRC

* Supported devices and production status are now determined automatically, to simplify support for future devices

* Enhanced support for IP Integrator

* No Functional changes.

AXI GPIO (2.0)

* Version 2.0 (Rev. 7)

* Updated IP to get Bus Width from common utilities for Board.

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI HWICAP (3.0)

* Version 3.0 (Rev. 8)

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI IIC (2.0)

* Version 2.0 (Rev. 8)

* Supported devices and production status are now determined automatically, to simplify support for future devices

* Enhanced support for IP Integrator

AXI Interconnect (2.1)

* Version  (Rev. -1)

* Update IP Integrator automation Tcl to accommodate changes to find_bd_objs IP integrator command.  No functional changes.

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI Interrupt Controller (4.1)

* Version 4.1 (Rev. 3)

* Updated to not use unimplemented synthesis features, no functional changes

* Corrected automatic parameter calculation for vector interrupt inputs

* Avoid warnings by only generating clock constraints when fast interrupt is used

* Avoid warnings by only updating the default value for IVAR registers when fast interrupt is used

* Added support for additional UltraScale devices

* Enabled out-of-context clock frequency setting

AXI Lite IPIF (3.0)

* Version 3.0 (Rev. 2)

* Timeout now generated for the transaction that is under progress

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI MMU (2.1)

* Version 2.1 (Rev. 3)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface CLKIF

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI Master Burst (2.0)

* Version 2.0 (Rev. 6)

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI Memory Mapped To PCI Express (2.6)

* Version 2.6

* Added support for RP example design

* Added support for shared logic in RP

* Added ffv1156, fbv484, fbv676 packages support

* Added PIPE simulation support for EP and RP example designs

* Replaced PCIe Gen2 Streaming core files in Endpoint example design with Root Port model files consisting of dsport and usrapp

* Added Transceiver debug and status port txinhibit as a part of EOU item

AXI Memory Mapped to Stream Mapper (1.1)

* Version 1.1 (Rev. 4)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface CLKIF

* Updated internal instantiation to axis_switch to match axis_switch updates.  No functional changes.

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI Performance Monitor (5.0)

* Version 5.0 (Rev. 6)

* Issue of handling read metric calculation when outstanding transactions is fixed

* Trigger and AXI Debug features are added

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interfaces

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI Protocol Checker (1.1)

* Version 1.1 (Rev. 6)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface aclk

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

* Fixed early triggering of pc_asserted[29] (MAX_W_WAITS).

AXI Protocol Converter (2.1)

* Version 2.1 (Rev. 5)

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI Quad SPI (3.2)

* Version 3.2 (Rev. 3)

* Example Design XDC updated to fix DRC

* No Functional changes.

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI Register Slice (2.1)

* Version 2.1 (Rev. 5)

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface CLKIF

AXI TFT Controller (2.0)

* Version 2.0 (Rev. 8)

* Example Design XDC updated to fix DRC warning

* No Functional changes.

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI Timebase Watchdog Timer (2.0)

* Version 2.0 (Rev. 7)

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI Timer (2.0)

* Version 2.0 (Rev. 7)

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI Traffic Generator (2.0)

* Version 2.0 (Rev. 6)

* Updated IP to have a new parameter to take transaction repeat number from user for Fixed_Repeat_Delay mode

* Updated IP to generate AWVALID and WVALID together in Advanced mode

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface CLOCK

* Supported devices and production status are now determined automatically, to simplify support for future devices

* Enhanced support for IP Integrator

AXI UART16550 (2.0)

* Version 2.0 (Rev. 7)

* Supported devices and production status are now determined automatically, to simplify support for future devices

* Enhanced Support for IP Integrator

AXI USB2 Device (5.0)

* Version 5.0 (Rev. 6)

* Fixed bd.tcl to reduce warnings in IPI design validation

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to all clocks

* Fixed post synthesis CDC warnings

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI Uartlite (2.0)

* Version 2.0 (Rev. 8)

* Supported devices and production status are now determined automatically, to simplify support for future devices

* Enhanced support for IP Integrator

AXI Video Direct Memory Access (6.2)

* Version 6.2 (Rev. 3)

* Support for up to 64 bit address

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI Virtual FIFO Controller (2.0)

* Version 2.0 (Rev. 7)

* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI-Stream FIFO (4.1)

* Version 4.1 (Rev. 2)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI4-Stream Accelerator Adapter (2.1)

* Version 2.1 (Rev. 3)

* Added synchronizers to support multiple clocks in the core

* Supported devices and production status are now determined automatically, to simplify support for future devices

AXI4-Stream Broadcaster (1.1)

* Version 1.1 (Rev. 5)

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI4-Stream Clock Converter (1.1)

* Version 1.1 (Rev. 6)

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

* The core XDC constraints are updated to omit datapath constraints if AXI4-Stream signal set results in 0 data width FIFOs.

AXI4-Stream Combiner (1.1)

* Version 1.1 (Rev. 4)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface CLKIF

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI4-Stream Data FIFO (1.1)

* Version 1.1 (Rev. 6)

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

* The core XDC constraints are updated to omit datapath constraints if AXI4-Stream signal set results in 0 data width FIFOs.

AXI4-Stream Data Width Converter (1.1)

* Version 1.1 (Rev. 4)

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface CLKIF

AXI4-Stream Interconnect (2.1)

* Version 2.1 (Rev. 5)

* Update IP Integrator automation Tcl to accommodate changes to find_bd_objs IP integrator command.  No functional changes.

* Added optional bus interface S_AXI_CTRL and optional ports S_AXI_CTRL_ACLK and S_AXI_CTRL_ARESETN, present when ROUTING_MODE == 1

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI4-Stream Protocol Checker (1.1)

* Version 1.1 (Rev. 5)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface CLKIF

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI4-Stream Register Slice (1.1)

* Version 1.1 (Rev. 5)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface CLKIF

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

* Internal register slice improvements to reduce fanout on input ready signal.

AXI4-Stream Subset Converter (1.1)

* Version 1.1 (Rev. 5)

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI4-Stream Switch (1.1)

* Version 1.1 (Rev. 5)

* Static routing mode option added.

* Added new arbiter algorithm: True Round-Robin. This algorithm implements a more accurate round-robin if not all ports are active.

* The support status for Kintex UltraScale is changed from Pre-Production to Production.

AXI4-Stream to Video Out (3.0)

* Version 3.0 (Rev. 7)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter for clock interfaces

* Kintex UltraScale production support

Accumulator (12.0)

* Version 12.0 (Rev. 6)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

Adder/Subtracter (12.0)

* Version 12.0 (Rev. 6)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

Aurora 64B66B (10.0)

* Version 10.0

* Added support for 7-series devices with FFV and FBV Pb-Free RoHs packages

* Max line rate support of 16.375G added for UltraScale GTH devices

* Added support for Simplex Auto recovery

* Added txinhibit and pcsrsvdin optional transceiver control and status ports

* Both pma_init and reset_pb ports made asynchronous to the core; reset, tx_reset and rx_reset input ports removed

* Standard CC module made part of the IP, do_cc port removed

* Flow control axi ports grouped into AXI4 Stream interfaces

* Control and status ports are grouped as display interfaces

* Added support for single ended clocking option to INIT_CLK and GTREFCLK

* Added support for contiguous lane selection for UltraScale devices

* CRC resource utilization optimized

* GT Reference Clocks, User Clock and Sync Clock ports updated with expected frequency values in IP-Integrator

* Line rate value restricted to 4 decimal digits for UltraScale devices

* INIT clock frequency value restricted to 6 decimal digits

Aurora 8B10B (11.0)

* Version 11.0

* Added support for 7 Series devices with FFV and FBV Pb-Free RoHs package

* Added txinhibit and pcsrsvdin optional transceiver control and status ports

* Both reset and gt_reset ports made asynchronous to the core

* Standard CC module made part of IP, do_cc and warn_cc ports removed

* Flow control ports grouped into AXI4 Stream interfaces

* Control and status ports are grouped as display interfaces

* Added support for single ended clocking option to INIT_CLK and GTREFCLK

* Added support for contiguous lane selection for UltraScale devices

* CRC resource utilization optimized

* GT Reference Clocks, User Clock and Sync Clock ports updated with expected frequency values in IP-Integrator

* Line rate value restricted to 4 decimal digits for UltraScale devices

* INIT clock frequency value restricted to 6 decimal digits

Binary Counter (12.0)

* Version 12.0 (Rev. 6)

* GUI update, no functional changes. Latency and Feedback Latency restricted when SSET or SINIT are true as well as when respective configurations are Automatic.

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

Block Memory Generator (8.2)

* Version 8.2 (Rev. 5)

* Delivering non encrypted behavioral models

* Supported memory depth is increased up to 1M words

* Added the power saving feature (RDADDRCHG) for UltraScale devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

CIC Compiler (4.0)

* Version 4.0 (Rev. 7)

* Restrict maximum oversampling rate to avoid integer overflow in HDL.

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

CORDIC (6.0)

* Version 6.0 (Rev. 7)

* Correction made to the bus interface data type definition TCL.

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

CPRI (8.4)

* Version 8.4

* Updated to use version 1.5 of the UltraScale GT Wizard.

* Removed redundant core parameters c_use_block_level and c_dual_tile.

* Added support for GTY Transceivers.

* Added optional support for real time vendor specific data bits in 10.1376Gps capable cores.

* Provided access to all CPRI control channels.

* Changed from the synchronous gearbox to the asynchronous gearbox to save clocking resources in UltraScale devices.

* Removed the clk_316_in and refclk2 ports from UltraScale 10.1376Gbps capable cores.

* Synchronized the loss of light input into the recovered clock domain.

* Added the gt_pcsrsvdin port to the UltraScale transceiver debug ports.

* Fixed 10.1376Gbps auto-negotiation.

* Added software reset feature.

* Added registers on the transceiver data outputs of 3.072Gbps capable Artix-7 cores to aid timing closure.

Chroma Resampler (4.0)

* Version 4.0 (Rev. 6)

* Support for Kintex UltraScale devices at Production status

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interfaces aclk_intf and s_axi_aclk_intf

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

Clocking Wizard (5.1)

* Version 5.1 (Rev. 6)

* Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

Color Correction Matrix (6.0)

* Version 6.0 (Rev. 7)

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface s_axi_aclk aclk

Color Filter Array Interpolation (7.0)

* Version 7.0 (Rev. 6)

* Support for Kintex UltraScale devices at Production status

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interfaces aclk_intf and s_axi_aclk_intf

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

Complex Multiplier (6.0)

* Version 6.0 (Rev. 7)

* Bugfix for four-multiplier 54x60 configuration which failed to elaborate due to an array width mismatch

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

Convolution Encoder (9.0)

* Version 9.0 (Rev. 7)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

DDS Compiler (6.0)

* Version 6.0 (Rev. 8)

* C model updated to increase maximum Frequency Resolution from 10kHz to 125MHz.

* Performance improved for cases above SFDR of 120dB or output width 20bits.

* C model bugfix for situation where accumulator width could differ by 1 bit from that used by the IP core.

* Addition of Beta support for future devices

* Additional parameter checking added to C model

* Supported devices and production status are now determined automatically, to simplify support for future devices

* GUI behavior changed so that Phase_Out appears by default when both phase_generator and sin_cos lut are selected

* GUI changed to add explicit error message for out-of-range System clock.

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

DSP48 Macro (3.0)

* Version 3.0 (Rev. 8)

* Addition of Beta support for future devices

* Correction to C register selection for configurations using RNDSIMPLE or RNDSYM instructions in combination with the Expert pipelining mode.

* Correction to fabric implementation to disable combinatorial feedback when P register is disabled.

* Supported devices and production status are now determined automatically, to simplify support for future devices

DUC/DDC Compiler (3.0)

* Version 3.0 (Rev. 7)

* GUI change to restrict unsupported configurations, RF sample rates of 30.72Mhz or 46.08Mhz when a 20Mhz LTE channel has been selected

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

* Sub-core HDL updated to resolve placement issues, no functional change

Discrete Fourier Transform (4.0)

* Version 4.0 (Rev. 7)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

DisplayPort (6.0)

* Version 6.0

* Updated audio interface for 3 to 8 channel Support, Removed SPDIF IP

* Added UltraScale GTH device support

* Added low power device support

* Fixed the RX alignment issue in Audio for 32-bit GT data width

* Provided the SW control to the RX VCPayload table

* Added propagate tcls for lnk_clk and lnk_clk_ibufds_out

* Updated Video, clock and reset interfaces as per IPI guidelines

* Improved IP Timing constraints(XDC), added MAX_DELAY constraints for better placement of the cells

* Added 8b10b enable control through SW in TX

* Increased the GT debug ports width with addition of new debug signals

Distributed Memory Generator (8.0)

* Version 8.0 (Rev. 8)

* Delivering unencrypted simulation files.

* Supported devices and production status are now determined automatically, to simplify support for future devices

Divider Generator (5.1)

* Version 5.1 (Rev. 6)

* GUI Fix. When using High Radix Divisor Width restricted to a range of [4-64]. No functional change.

* Non-functional change to bip_sdivider_synth.vhd to fix low latency cases of the LutMult architecture.

* Add Matlab MEX wrapper for the C model.

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

ECC (2.0)

* Version 2.0 (Rev. 8)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface MY_CLOCK

* Supported devices and production status are now determined automatically, to simplify support for future devices

Ethernet PHY MII to Reduced MII (2.0)

* Version 2.0 (Rev. 7)

* Example Design XDC updated to fix DRC

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface CLOCK.

* Supported devices and production status are now determined automatically, to simplify support for future devices

* No functional changes.

FIFO Generator (12.0)

* Version 12.0 (Rev. 4)

* Delivering  non encrypted behavioral models.

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports

* Enabling behavioral simulation for Built-in FIFO configurations changes the simulation file names and delivery structure.

* Supported devices and production status are now determined automatically, to simplify support for future devices

FIR Compiler (7.2)

* Version 7.2 (Rev. 2)

* Warning reduction.

* Correction to single rate half-band control for data vector reset, an oversample rate of 2, utilizing a single multiply add unit.

* Added the SRL_STYLE attribute to the delay component to ensure an efficient implementation.

* Fix to Sample Period propagation to avoid false Column Configuration errors.

* GUI filter coefficient processing speed up for bit widths greater than DSP48 input width.

* Addition of Beta support for future devices

* Correction to fractional interpolation configurations utilizing Maximum Possible hardware oversampling specification in System Generator.

* Update to C model to match GUI behavior. Add support for quantization/truncation of integer only coefficients when XIP_FIR_QUANTIZED_ONLY has been specified.

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

Fast Fourier Transform (9.0)

* Version 9.0 (Rev. 7)

* Bugfix for occasional (data-dependent) incorrect Block Exponent output in Radix-2 Lite architecture

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

Fixed Interval Timer (2.0)

* Version 2.0 (Rev. 5)

* Added support for additional UltraScale devices

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface

Floating-point (7.0)

* Version 7.0 (Rev. 8)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

* Sign bit of NaNs returned by _flt and _d functions is now zero (positive) to be consistent with other xip_fpo functions and RTL behavior when performing direct bitwise comparisons

G.709 FEC Encoder/Decoder (2.1)

* Version 2.1 (Rev. 5)

* Adoption of new GUI API. component.xml and g709_fec_v2_1.tcl altered. No functional change.

* Addition of Beta support for future devices

G.975.1 EFEC I.4 Encoder/Decoder (1.0)

* Version 1.0 (Rev. 8)

* Internal GUI updates. No functional Changes

* Addition of Beta support for future devices

G.975.1 EFEC I.7 Encoder/Decoder (2.0)

* Version 2.0 (Rev. 8)

* Internal GUI updates. No functional Changes

* Addition of Beta support for future devices

Gamma Correction (7.0)

* Version 7.0 (Rev. 7)

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter

Gmii to Rgmii (4.0)

* Version 4.0

* Adding 90 deg phase shift option

High Speed SelectIO Wizard (1.1)

* Version 1.1 (Rev. 2)

* Bidirectional bus support enabled for one interface without example simulation support

IBERT 7 Series GTH (3.0)

* Version 3.0 (Rev. 8)

* Added device support for new FFV and FBV packages.

IBERT 7 Series GTP (3.0)

* Version 3.0 (Rev. 8)

* Fixed TIMING-10 DRC issue.

* Added Device support for new FBV and FFV packages.

IBERT 7 Series GTX (3.0)

* Version 3.0 (Rev. 8)

* Added Device Support for new FBV and FFV packages

IBERT 7 Series GTZ (3.1)

* Version 3.1 (Rev. 6)

* Fixed TIMING 29 DRC warnings.

IBERT UltraScale GTH (1.2)

* Version 1.2

* Changed minor version.

* Removed System clock and RXOUT clock N pin tab from GUI.

* Renamed some model parameter names.

* Fixed the issue of underreporting number of errors.

IBERT UltraScale GTY (1.1)

* Version 1.1

* Changed minor version.

* Removed System clock and RXOUT clock N pin tab from GUI.

* Renamed some model parameter names.

* Fixed the issue of underreporting number of errors.

IEEE 802.3bj RS-FEC (1.0)

* Version 1.0

* First version of core

ILA (Integrated Logic Analyzer) (5.1)

* Version 5.1

* Fixed example design placer issue with pin location constraints for SVD packages

IOModule (3.0)

* Version 3.0 (Rev. 1)

* Updated IP to get Bus Width from common utilities for Board

* Reduce synthesis warnings, no functional changes

* Added support for additional UltraScale devices

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface

Image Enhancement (8.0)

* Version 8.0 (Rev. 7)

* Support for Kintex UltraScale devices at Production status

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interfaces aclk_intf and s_axi_aclk_intf

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

Interlaken (1.5)

* Version 1.5

* LANE 1 support for all the lane rates

* OOBFC 32,64 and 20148 calendar length support with 12 Lanes

* Burstshort all the possible values support for all the BURSTMAX values

Interleaver/De-interleaver (8.0)

* Version 8.0 (Rev. 6)

* GUI updated to ensure that Block Type Size can not be set to Variable when Row or Column Permutations are in use

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

JESD204 (6.1)

* Version 6.1

* Functionality and width of 'lanes in use' register has changed. This register can now be used to activate or deactivate a specific lane. See PG066 for more information

* Added support for configurable lane IDs. See PG066 for more information

* Fixed issue where RX data was not aligning to the LMFC crossing when Multiframe size was not a multiple of 4

* Fixed issue with buffer overflow register not indicating an overflow correctly

* Fixed issue in Tx configurations with SYSREF ALYWAYS set to '0'. If a loss of SYNC occurred, the LMFC counters were aligning to every SYSREF pulse

* Fixed issue in Subclass 2 configurations where output alignment was incorrect when the Multiframe size was not a multiple of 4

* Fixed issue with Rx Link Error Status Registers (0x01C and 0x03C) not auto clearing after a read for multi-lane designs

* Added GUI option to configure AXI4-Lite Management Interface Clock

* Added debug port gt*_txinhibit_in. This will affect 7-Series designs with Transceiver Debug enabled

* Added debug ports gt_txinhibit and gt_pcsrsvdin. This will affect all UltraScale designs with Transceiver Debug enabled

* Changed default vaule of Watchdog Timer Disable register from '0' to '1'

* Added gt_rxbufreset to GUI symbol. This will affect UltraScale designs with Transceiver Debug enabled.

JESD204 PHY (2.0)

* Version 2.0

* Added optional AXI4-Lite Management Interface.

* Fixed issue where tx and rx gt_reset inputs were resetting the entire Transceiver and not the individual TX or RX paths

* Added debug port gt*_txinhibit_in. This will affect 7-Series designs with Transceiver Debug enabled

* Added debug ports gt_txinhibit and gt_pcsrsvdin. This will affect all UltraScale designs with Transceiver Debug enabled

* For UltraScale devices fixed issue where QPLL0 and QPLL1 resets were tied together. This port change will affect designs with Shared Logic in Example Design

* Added gt_rxbufreset to GUI symbol. This will affect UltraScale designs with Transceiver Debug enabled.

JTAG to AXI Master (1.0)

* Version 1.0 (Rev. 7)

* AXI_WRITE_DONE status flag to remain asserted until issuance of a new write command

* Updated soft reset logic to reset control registers and FIFOs

* Added logic to halt wr/rd transactions in case of errors while executing queued transactions

* For queued transaction, done flags are asserted after the completion of all the queued up transaction instead of assertion after every individual transaction

* Concurrent assertion of awvalid and wvalid signals

* Removed ooc_xdc.ttcl file reference from coreinfo

LMB BRAM Controller (4.0)

* Version 4.0 (Rev. 6)

* Updated C_MASK calculation to take into account if the connected processor is a lockstep slave.

* Added support for additional UltraScale devices

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interfaces

LTE DL Channel Encoder (3.0)

* Version 3.0 (Rev. 7)

* Internal GUI updates. No functional Changes

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

LTE Fast Fourier Transform (2.0)

* Version 2.0 (Rev. 7)

* Internal GUI updates.  No functional changes.

* Bugfix for segmentation fault when using Matlab MEX wrapper on 32-bit Windows platforms.

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

LTE PUCCH Receiver (2.0)

* Version 2.0 (Rev. 7)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

LTE RACH Detector (2.0)

* Version 2.0 (Rev. 7)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

* Sub-core HDL updated to resolve placement issues, no functional change

LTE UL Channel Decoder (4.0)

* Version 4.0 (Rev. 7)

* Internal GUI updates.  No functional changes.

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

Local Memory Bus (LMB) 1.0 (3.0)

* Version 3.0 (Rev. 6)

* Added support for additional UltraScale devices

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface

Mailbox (2.1)

* Version 2.1 (Rev. 3)

* Added support for additional UltraScale devices

* Enabled out-of-context clock frequency setting

Memory Interface Generator (MIG 7 Series) (2.3)

* Version 2.3 (Rev. 1)

* Enhanced RLDRAM II and RLDRAM 3 controller efficiency.

* Resolved DDR2/DDR3 issue where additional BUFG added in "opt_design" for the "freq_refclk" can lead to minimum pulse width timing violations. See (Xilinx Answer 63165) for details.

* Resolved issue with Virtex-7 HT where error is generated when trying to open the MIG 7 Series tool when targeting a part with an flg package - Failed to generate custom UI outputs.  See (Xilinx Answer 60527) for details.

* Resolved issues with DDR3/DDR2 where Manual Window Check feature does not work with VIO 2.0.  See (Xilinx Answer 59284) for details.

* Resolved issue with the "No Buffer" option always expecting a 200MHz on clk_ref_i and instantiates additional MMCM for 300 or 400MHz. See (Xilinx Answer 63227) for details.

* Resolved issue with CRITICAL WARNING message when multiple MIG IP are added to the same project.  See (Xilinx Answer 58621) for details.

Memory Interface Generator (MIG) (7.0)

* Version 7.0

* Moved I/O Planning task from IP to Vivado

* Vivado supports pin planning and bank sharing for multiple controllers

* Memory IP related I/Os will not appear in updated design. See the update.log for instructions on migrating I/O constraints.

* Added XSIM simulator support

* Added simulation support in Vivado project

* Added support for x4 and x8 RDIMM parts for DDR3 and DDR4

* Added support for twin-die parts for DDR3 and DDR4

* Added support for Read Latency '2' parts for QDR2+

* Enablement of board automation in IPI

* Added DDR4/3 support for user request controller options (ZQ calibration, refresh, and auto-precharge)

* Advanced Traffic Generator support for DDR3 and DDR4

* Fast simulation Model(BFM) support for all interfaces

* Create Custom part selection support for all interfaces

* Added System Clock No Buffer support to allow clock sharing for multi-instance designs

* Added generation of Micron Memory Simulation Models

* Resolved multi-driver errors.  See Xilinx Answer 63261.

* Resolved DDR4/3 tCCD and tRTW violations.  See Xilinx Answer 62930.

* Resolved DDR4/3 dual rank address mirror issues.  See Xilinx Answer 63022.

* Resolved timing errors for all interfaces.  See Xilinx Answer 62774.

* Resolved DDR4/3 pin generation errors when not all byte lanes are assigned.  See Xilinx Answer 62649.

* Resolved 64-bit DDR3 issue in generating output products.  See Xilinx Answer 60528.

* Resolved Critical warnings with multiple MIG instances.  See Xilinx Answer 59989.

* Resolved RLDRAM3 timing failures in mmcm_clkout0 domain.  See Xilinx Answer 63238.

MicroBlaze (9.5)

* Version 9.5

* Added support for 16 word cache lines

* Added support for optional imprecise ECC exceptions to improve QoR

* Improved detection of lockstep master for DRC in lockstep slave

* Added support for additional UltraScale devices

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface

* Set outstanding reads to 1 for AXI cache interfaces when the data width is 128 bits, 256 bits or 512 bits

* Ensure that distributed RAM is not used when C_AVOID_PRIMITIVES is set to 2 or 3. Versions that have this issue: 9.0, 9.1, 9.2, 9.3, 9.4.

* If parameters C_DCACHE_ALWAYS_USED and C_ICACHE_ALWAYS_USED are not set, use peripheral AXI interfaces for memory accesses within the cacheable address range when caches are disabled. Versions that have this issue: 9.0, 9.1, 9.2, 9.3, 9.4.

* Fixed behavioral simulation stall due to uninitialized internal debug signal. Versions that have this issue: 9.4. Can only occur when debug and area optimization are not enabled.

* Set debug status correctly for sleep after reset. Versions that have this issue: 9.4. Can only occur when debug is enabled and using Reset_Mode.

MicroBlaze Debug Module (MDM) (3.2)

* Version 3.2 (Rev. 2)

* Added support for additional UltraScale devices

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface

MicroBlaze MCS (2.3)

* Version 2.3

* Added support for additional UltraScale devices

* Updated with latest subcore versions

* Updated IP to get Bus Width from common utilities for Board

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface

Multiplier (12.0)

* Version 12.0 (Rev. 7)

* Rephrased RTL to work around range checking issue when simulating with Vivado Simulator.  No functional changes.

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

* Modified constant-coefficient multiplier distributed ROM RTL for consistency with Vivado Synthesis inference template.  No functional changes.

Multiply Adder (3.0)

* Version 3.0 (Rev. 6)

* GUI no longer allows Output MSB and Output LSB values greater than 48 when the input widths are such that the generated core can fit on a single DSP48

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

Mutex (2.1)

* Version 2.1 (Rev. 3)

* Added support for additional UltraScale devices

Partial Reconfiguration Controller (1.0)

* Version 1.0

* Initial Release

Peak Cancellation Crest Factor Reduction (6.0)

* Version 6.0

* New smart peak processing added to enable inputs at 1.2 x iBW

* New post processing stage to support optional hard clipper or WCFR

* WCFR stage is mandatory in post processing stage when Smart Peak Processing is enabled

* Support for WCFR standalone mode (without PC-CFR)

* Support of data-rate 8 added

* Supports data-width of 16 and 18 bits only

* New AXI4-Stream control channel for dynamic mode

* New CFR statistics registers and version register added

* Read back support for all AXI4-Lite registers

* Read back support for base CPs in dynamic mode

* Support for C model has been removed, MATLAB(R) model can be downloaded from the PC-CFR evaluation lounge

* Improved resource utilization and better QoR

* Supported devices and production status are now determined automatically, to simplify support for future devices

Processor System Reset (5.0)

* Version 5.0 (Rev. 7)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to slowest_sync_clk

* Supported devices and production status are now determined automatically, to simplify support for future devices

QSGMII (3.3)

* Version 3.3

* Uprev of UltraScale wizard to version 1.5.

* Transceiver control and status ports: added gt_txinhibit and gt_pcsrsvdin[]

* Added widgets to the core GUI to allow per-core-instance Transceiver and Reference Clock placement selection for UltraScale devices

* Changed version of helper core gig_ethernet_pcs_pma from v14_3 to v15_0

RAM-based Shift Register (12.0)

* Version 12.0 (Rev. 6)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

RGB to YCrCb Color-Space Converter (7.1)

* Version 7.1 (Rev. 5)

* Kintex UltraScale moving from pre-production to production

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface s_axi_aclk aclk

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

RXAUI (4.3)

* Version 4.3

* Kintex UltraScale Production support

* Added support for Virtex UltraScale GTYE3 transceivers

* For UltraScale devices, added an option to select the transceiver reference clock frequency used by the core: select from 125MHz, 156.25MHz or 312.5MHz

* For UltraScale devices, added GUI options to select per-core-instance Transceiver locations

* For UltraScale devices, issuing a transceiver GTRXRESET after entering near-end loopback and switching the loopback mode to near-end PCS loopback

* Added a GUI option to enter the transceiver DRP clock frequency used by the core

* When the transceiver Rx PRBS functionality is enabled through the optional transceiver control and status ports, periodic transceiver RX resets due to lack of lane alignment are inhibited

* Transceiver control and status ports: added gt_txinhibit and gt_pcsrsvdin[]

* Updated to use the latest GT UltraScale Wizard v1.5

* Updated to use the latest 7-Series Transceiver Wizard v3.5.

* For GTXE2 and GTHE2 7-Series transceivers, the Transceiver Wizard update includes a change in mode of the Rx Equalizer from DFE to LPM.

* For Automotive Artix-7 devices, fixed the clocking logic by adding a missing clock buffer between the TXOUTCLK from a transceiver and the MMCM.

Reed-Solomon Decoder (9.0)

* Version 9.0 (Rev. 8)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

Reed-Solomon Encoder (9.0)

* Version 9.0 (Rev. 7)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

S/PDIF (2.0)

* Version 2.0 (Rev. 8)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to all clocks

* Supported devices and production status are now determined automatically, to simplify support for future devices

SMPTE 2022-1/2 Video over IP Receiver (2.0)

* Version 2.0 (Rev. 2)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface tx*axis_aclk,sys_clk and s_axi_aclk

* Added support for new ports and parameter addition to Block Memory Generator v8.2

SMPTE 2022-1/2 Video over IP Transmitter (2.0)

* Version 2.0 (Rev. 2)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface s*_axis_clk,sys_clk and s_axi_aclk

* Added support for new ports and parameter addition to Block Memory Generator v8.2

SMPTE SD/HD/3G-SDI (3.0)

* Version 3.0 (Rev. 4)

* Update to the locking algorithm to reduce false locking when the cable is unplugged

SMPTE UHD-SDI (1.0)

* Version 1.0

* Initial release

SMPTE2022-5/6 Video over IP Receiver (5.0)

* Version 5.0

* Fixed sd_ce_cadence disruption when sdi_clk change

* Added logic in RX to discard non-UDP packet

* Added new port gtready to eliminate the need to perform sdi reset for TX clock change

* Fixed improper video output after input video stream is cut

* Fixed for rtp_pkt_buffered at the core interface going to 0 during pkt_locked

* Fixed for incorrect buffer depth at sequence number and timestamp rollover during synchronous drop and delay

* Added support for new ports and parameter addition to block memory generator v8.2

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface

* Fixed for incorrect missing packet counter increasing due to timestamp rollover

* Changed clk27m to be as data enable and renamed to ce_27m to align with the usage

SMPTE2022-5/6 Video over IP Transmitter (4.0)

* Version 4.0 (Rev. 2)

* Fixed secondary link IP header on incorrect TOS and TTL for RTP and FEC frame

* Fixed metastability in timestamp sampling

* Fixed SOF locking issue during SDI mode switching to SD

* Fixed header framecount field stays at 0 in SD mode

* Added support for new ports and parameter addition to block memory generator v8.2

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface

SPI-4.2 (13.0)

* Version 13.0 (Rev. 6)

* No changes

SelectIO Interface Wizard (5.1)

* Version 5.1 (Rev. 5)

* Updated the example design XDC to resolve the DRC warnings, no functional changes

Serial RapidIO Gen2 (3.3)

* Version 3.3

* Reduced transmit path latency by one clock in BUF layer(log_clk) and PHY layer(phy_clk) respectively

* Fixed functional issues around error injection and packet cancellation

* Updated GTH wrappers for current release

* Added fairness algorithm as user choice in GUI

* Transceiver control and status ports: added gt_txinhibit and gt_pcsrsvdin[]

Soft Error Mitigation (4.1)

* Version 4.1 (Rev. 4)

* Reduce SEM controller pblock dimensions for xc7a15 and xc7a50 to align to clock regions to improve logic packing and remove placer alignment warning.

* Remove empty example design text file, x7_sem_mon_fw_v.txt, from being generated in the example project. This file is unnecessary and has no functional impact.

System Cache (3.1)

* Version 3.1

* Added additional generic ports

* Increased optimized ports limit

* Support handling of 16 word cache lines with coherency enabled

* Support address width up to 64 bits

* Added support for additional UltraScale devices

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock interface

System Management Wizard (1.2)

* Version 1.2

* GUI Related Updates. No Functional Changes.

* Averaging feature is disabled in single pass mode as it is invalid case.

* I2C Interface Support is added for all SLRs in SSIT devices.

* Temperature calculation updated depending on Internal and external reference.

* Example Design support for I2C has been added.

Test Pattern Generator (6.0)

* Version 6.0 (Rev. 4)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter for clock interfaces

* Kintex UltraScale production support

Timer Sync 1588 (1.2)

* Version 1.2 (Rev. 2)

* No changes

Tri Mode Ethernet MAC (9.0)

* Version 9.0

* Kintex UltraScale parts moved to Production

* Added 2.5G Ethernet support and updated related constraints in XDC files

* For 2.5G added an clock port for AXI4-Lite I/F in Example Design. Updated Example Design clock module and relevant XDC files.

* For UltraScale devices in RGMII mode - Changed RX clocking to provide a dedicated clock to the Input DDR elements to ease timing closure on IOB paths and updated related XDC files

* For UltraScale devices in GMII mode - Changed RX clocking to provide a dedicated clock to the IOB elements to ease timing closure on IOB paths

* Updated Example Design XDC to provide sample LOC constraints for IOs and clock elements

* Fixed bug in AXI-Lite Interface which caused the system to hang for back-to-back reads; Updated Clock XDC file

* For UltraScale devices - Enabled sharing of IDELAYCTRL component

* The input clock port gtx_clk is not present when the core is configured in MII mode and Statistics feature is disabled. In this configuration the gtx_clk does not drive any load

* Removed 10/100 Mb/s license

* Fixed bug in Address Filter which caused the Unicast filter to be disabled when the Address Filter is enabled and the number of configurable filters is set to zero

* Updated the uniquification of clock names used in create_clock command in GMII/RGMII Clock XDC file. Uniquification is done using instance name

* Updated board support tab to include MDIO_RTL VLNV

* Added AXI4-Lite clock frequency field in GUI

UltraScale FPGAs Transceivers Wizard (1.5)

* Version 1.5 (Rev. 1)

* Added the ability to specify LPM or DFE for the equalization mode option in the Wizard customization GUI

* Added support for UltraScale -1LV speed grade devices

* Updated the status of some GTH transceiver configuration presets

* Modified connectivity between the reset controller helper block and CPLL resources in all GTY configurations and in GTH configurations targeting Virtex UltraScale ES2 devices, to drive CPLLPD instead of CPLLRESET in accordance with Xilinx UltraScale Architecture Transceivers user guides

* Improved performance of GTH and GTY transceivers via parameter updates

* Fixed a bug that caused context menu options in the channel graphic of the Wizard customization GUI Physical Resources tab to be incorrectly grayed out

* Kintex UltraScale production status is now determined automatically, to simplify support for future devices

UltraScale Soft Error Mitigation (2.0)

* Version 2.0 (Rev. 2)

* Public release of IP

* Hardware verification performed on production KU040, VU095 ES1, KU060 ES2, and KU115 ES2 devices

* All monolithic devices supported

UltraScale FPGA Gen3 Integrated Block for PCI Express (4.0)

* Version 4.0

* Upgraded GT wizard to 1.5 version.

* Modified the port width for m_axis_cq_tready and m_axis_rc_tready signals from 22 bits to 1 bit.

* Non-default ports startup_cfgclk, startup_cfgmclk, startup_di, startup_eos, startup_preq, startup_do, startup_dts, startup_fcsbo, startup_fcdbto, startup_gsr, startup_gts, startup_keyclearb, startup_pack, startup_usrdoneo, startup_usrcclko, startup_usrcclkts, startup_usrdonets to access the STARTUP primitive were added for Tandem configurations where the startup is internal to the core. The mcap_eos_out output was removed.

* Removed default ports cfg_vend_id, cfg_dev_id, cfg_rev_id and cfg_subsys_id since these signals get the parameter values from Vivado generated synth wrapper.

* Added a non-default input port gt_txinhibit to the transceiver debug interface.

* Added support for new packages: flvb1760,ffvd1517,ffvc1517,flva2104,flvd1517 and flvb2104

* Enabled Tandem and PR over PCIe support for xcku115, xcvu125, xcvu160, and xcvu190.

* The Tandem PCIe and Tandem PROM selections have been combined into a single Tandem selection. This resulted in minor changes to the RTL, constraints, and mcap_design_switch output behavior.

* PR over PCIe configurations no longer apply isolation muxing to the PCIe interface. Isolation for PR should be managed in the user design.

* Added GUI option to select PLL_TYPE for Gen2 Speed: CPLL (Optional) and QPLL1 (Default)

* Added GUI option to select CORE_CLK_FREQ for Gen3 x1/x2/x4: 250 MHz (Default) and 500 MHz (Optional)

* Edited Insertion loss default value to 15 db from 20 db.

* Made GTWIZARD as default for all configurations.

* Removed CPLL Calibration module for Production devices and for VU095-ES2.

* Added BUFG_GT_SYNC macro for sys_rst buffer.

* Added PL_SIM_FAST_LINK_TRAINING parameter in sim wrapper file to speed up simulation.

* Added bram_req_8k.v (REQUEST) and it has BRAM WE/RE related change.

* Added support for post synth/implementation netlist functional simulations for Endpoint and Verilog/VHDL only configurations. It is not supported for Rootport configuration and External PIPE mode simulations in this release.

* Removed the user parameter for 64bit enablement for BAR1 and BAR3.

* Removed support for 250 MHz user clock/axis for -1LV speedgrade

VIO (Virtual Input/Output) (3.0)

* Version 3.0 (Rev. 7)

* Added synchronizer for cdc

Video Deinterlacer (4.0)

* Version 4.0 (Rev. 8)

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

* Enabled out-of-context clock frequency setting by adding FREQ HZ parameter to clock interface

Video In to AXI4-Stream (3.0)

* Version 3.0 (Rev. 7)

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter for clock interfaces

* Kintex UltraScale production support

Video On Screen Display (6.0)

* Version 6.0 (Rev. 8)

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter

Video Scaler (8.1)

* Version 8.1 (Rev. 5)

* Support for Kintex UltraScale devices at Production status

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

Video Timing Controller (6.1)

* Version 6.1 (Rev. 5)

* Fixed vertical timing generation issue when generator clock enable is toggled

* Fixed field-id timing generation issue when switching between progressive and interlaced

* Fixed redundant ASYNC_REG attribute to reduce synthesis warning

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter for clock interfaces

* Kintex UltraScale production support

Video over IP FEC Receiver (1.0)

* Version 1.0

* Initial release

Video over IP FEC Transmitter (1.0)

* Version 1.0

* Initial release

Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.0)

* Version 4.0

* Modified the width of m_axis_cq_tready and m_axis_rc_tready from 22 bits to single bit.

* Added non-default input port pipe_txinhibit.

* Added support for FLG packages for xc7vh580t and xc7vh870t devices.

* Added shared logic support for RP configuration.

* Modified the External Pipe Interface as Master for Rootport configuration and Slave for Endpoint and Legacy Endpoint configurations.

* Reduced BUFG usage by 1.

Viterbi Decoder (9.1)

* Version 9.1 (Rev. 2)

* Addition of Beta support for future devices

* Supported devices and production status are now determined automatically, to simplify support for future devices

XADC Wizard (3.0)

* Version 3.0 (Rev. 7)

* GUI Updates, no functional changes

XAUI (12.2)

* Version 12.2

* Kintex UltraScale Production support

* Added support for Virtex UltraScale GTYE3 transceivers

* For UltraScale devices, added an option to select the transceiver reference clock frequency used by the core: select from 125MHz, 156.25MHz or 312.5MHz

* For UltraScale devices, added GUI options to select per-core-instance Transceiver locations

* For UltraScale devices, issuing a transceiver GTRXRESET after entering near-end loopback and switching the loopback mode to near-end PCS loopback

* Added a GUI option to enter the transceiver DRP clock frequency used by the core

* When the transceiver Rx PRBS functionality is enabled through the optional transceiver control and status ports, periodic transceiver RX resets due to lack of lane alignment are inhibited

* Transceiver control and status ports: added gt_txinhibit and gt_pcsrsvdin[]

* Updated to use the latest GT UltraScale Wizard v1.5

* Updated to use the latest 7-Series Transceiver Wizard v3.5.

* For GTXE2 and GTHE2 7-Series transceivers, the Transceiver Wizard update includes a change in mode of the Rx Equalizer from DFE to LPM.

YCrCb to RGB Color-Space Converter (7.1)

* Version 7.1 (Rev. 5)

* C models are no longer provided for 32-bit operating systems as Vivado has deprecated 32-bit OS support

* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter

ZYNQ7 Processing System (5.5)

* Version 5.5 (Rev. 1)

* Added support and functionality  for Secure and Non-Secure

* Removed wire ENET0_GMII_TX_EN_i

* Wire  ENET0_GMII_TX_ER_i; and the signals were tied low

* Added functionality for TRACE_CTL_PIPE

* Secure/Non-Secure Access configuration Enablement added in General settings

* DDR training board details were updated with revised scale and correct values

* Writing to register tpiu  Curentsize (0xF8803004) register is removed if trace is disabled

* Dynamic Trace Pipeline width configuration based on user choice

* Adding keep option for Trace Control & Data registers

* If JTAG OBUF is disabled; the PJTAG_TDO is set to 0

ZYNQ7 Processing System BFM (2.0)

* Version 2.0 (Rev. 3)

* No changes

axi_sg (4.1)

* Version 4.1 (Rev. 1)

* AXI SG to support 64bit address BD

* Supported devices and production status are now determined automatically, to simplify support for future devices

interrupt_controller (3.1)

* Version 3.1 (Rev. 1)

* Supported devices and production status are now determined automatically, to simplify support for future devices

lib_bmg (1.0)

* Version 1.0 (Rev. 1)

* Updated the top file to have new ports as per BMG changes

* Supported devices and production status are now determined automatically, to simplify support for future devices

lib_cdc (1.0)

* Version 1.0 (Rev. 1)

* Supported devices and production status are now determined automatically, to simplify support for future devices

lib_fifo (1.0)

* Version 1.0 (Rev. 1)

* Supported devices and production status are now determined automatically, to simplify support for future devices

lib_pkg (1.0)

* Version 1.0 (Rev. 1)

* Supported devices and production status are now determined automatically, to simplify support for future devices

lib_srl_fifo (1.0)

* Version 1.0 (Rev. 1)

* Supported devices and production status are now determined automatically, to simplify support for future devices

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
63402 JESD204 v6.0 - Rx Link Error Status auto-clear issue N/A N/A
AR# 64619
Date Created 05/20/2015
Last Updated 10/01/2015
Status Active
Type Release Notes
Tools
  • Vivado Design Suite