Version Found: RLDRAM3 v7.0
Version Resolved: See (Xilinx Answer 69037)
When migrating a MIG UltraScale RLDRAM3 IP to 2015.1, a DDR4 controller can mistakenly be created instead of RLDRAM3.
This only occurs when the "sys_rst" port is not assigned to an I/O site in the original MIG UltraScale RLDRAM3 IP.
If this issue occurs you must regenerate a new MIG UltraScale RLDRAM3 IP in Vivado 2015.1 to ensure that the proper interface type and the rest of the IP parameters are generated properly.
See (Xilinx Answer 63831) for guidance on Migrating and Upgrading IP into 2015.1.
05/21/2015 - Initial Release