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AR# 64653

Virtex UltraScale Integrated Block for 100G Ethernet - CAUI-4 - Cannot implement CAUI-4 with CAUI X0Y0 location in XCVU095-2FFVA1760E


I cannot implement a fourth channel 100G Ethernet (CAUI-4) based on XCVU095-2FFVA1760E.

According to the product table there should be 4*100G Ethernet hard IP on the board.

1. I am using the Default parameters, with mode set to CAUI 10:


2. I can select one of four cores in this mode.


3. I Change settings to CAUI 4:


4. I can now only select one of three cores:



CAUI4 requires GTY transceivers (as it runs at 25G) while CAUI10 can target either GTH or GTY transceivers.

The CMAC site X0Y0 does not support connection to GTY transceivers in this part and package as the lower GTYs in the same clock region, or one above or below are not bonded. 

As Per( PG165), CAUI-4 has the following Transceiver Selection rules:

  • CAUI-4 GTs have to be contiguous
  • CAUI-4 must use the same CR or one above or below
  • All GTs must come from the same GT quad
  • CAUI-4 is only supported in Lanes 1-4
  • CAUI-4 must be implemented within an SLR

If you check the above example in the device view, the lower GTYs are not bonded in that package:

AR# 64653
Date 06/26/2015
Status Active
Type General Article
  • Virtex UltraScale
  • Vivado Design Suite - 2015.1
  • 40G/100G Ethernet Core
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