Version Found: MIG 7 Series v2.3
Version Resolved: See (Xilinx Answer 54025)
Max data widths for DDR3/DDR2 interfaces for the following FPGA devices have limitations:
For the above FPGAs, the MIG GUI might show the maximum data widths given in A-1 below, but the true data widths should be noted as given in A-2:
Even though the MIG GUI allows A-1 data widths during selection of the data width drop down list and in the bank selection pages, you cannot generate the designs for those data widths as pinout allocation is not feasible.
For example, consider FTG256 FPGA which has 2 banks (14 and 15) which have a total 7 byte lanes for memory selection (byte lane 0 of bank 14 has PUDC pins, and so cannot be used).
Out of 7 byte lanes, 3 bytes are needed for address and control and the remaining 4 bytes for data width, which corresponds to 32 bits.
Even with one or two pin optimization in the Address and Control bank, we still require 3 byte lanes for Address and Control and only 4 byte lanes remain for Data.
As a result, data width is limited to 32.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem also exists in earlier versions, but is not specific testing has been performed to verify earlier versions.
05/22/2015 - Initial Release