We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64655

DDR3 UltraScale - Dual Rank RDIMM - IP generation incorrectly enables address mirroring for dual rank DDR3 RDIMMs


Version Found: v7.1
Version Resolved: (Xilinx Answer 58435)

Address Mirroring is not supported for DDR3 Dual Rank RDIMM parts.

However, upon IP generation, the CA_MIRROR parameter is enabled (set to ON) for these parts.


To work around this issue, the patch attached to this answer record must be installed to the Vivado 2015.1 install location.

Please download the patch and follow the patch installation instructions included within the AR64655_Vivado_2015_1_preliminary_rev1.zip\vivado\patch_readme\AR64655_Vivado_2015_1_preliminary_rev1.txt document.

The patch will disable the CA_MIRROR parameter for both rtl and simulation when a DDR3 dual rank RDIMM part is selected within the MIG tool.


Associated Attachments

Name File Size File Type
AR64655_Vivado_2015_1_preliminary_rev1.zip 1 MB ZIP
AR# 64655
Date Created 05/22/2015
Last Updated 05/26/2015
Status Active
Type Known Issues
  • Kintex UltraScale
  • Virtex UltraScale
  • MIG UltraScale