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AR# 64682

2015.1 UltraScale Partial Reconfiguration - Nested pblock with clockregion based range incorrecly triggers DRC HDPR-5


In a partial reconfiguration (PR) design targeting UltraScale devices, I am trying to use a nested pblock inside the PR pblock.

The nested pblock contains a CLOCKREGION-based range, and is called "pblock_rm_u1"

Place_design fails with the following error:

ERROR: [DRC 23-20] Rule violation (HDPR-5) Reconfigurable Pblocks must use valid types - Reconfigurable cell 'RM_u1' with Pblock 'pblock_rm_u1' uses the invalid type 'CLOCKREGION' to define the Pblock range. 
This type is only valid in static logic. 
Please remove this type from Pblock 'pblock_rm_u1'.
Resolution: add the missing ranges to the parent or child Pblock.

From Vivado 2015.1 on, a CLOCKREGION based range for a Reconfigurable Partition in an UltraScale Device is supported. 

Why does this DRC HDPR-5 still occur?


This DRC HDPR-5 should not be reported on the nested pblock and you can ignore it safely.

This issue is fixed in Vivado 2015.3.

AR# 64682
Date 08/26/2015
Status Active
Type General Article
  • Vivado Design Suite - 2015.1
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