In a partial reconfiguration (PR) design targeting UltraScale devices, I am trying to use a nested pblock inside the PR pblock.
The nested pblock contains a CLOCKREGION-based range, and is called "pblock_rm_u1"
Place_design fails with the following error:
From Vivado 2015.1 on, a CLOCKREGION based range for a Reconfigurable Partition in an UltraScale Device is supported.
Why does this DRC HDPR-5 still occur?
This DRC HDPR-5 should not be reported on the nested pblock and you can ignore it safely.
This issue is fixed in Vivado 2015.3.