We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64688

2015.1 UltraScale Partial Reconfiguration - DRC HDPR-31 is falsely reported in UltraScale devices


When I run the report_drc command on a partial reconfiguration design targeting UltraScale devices, DRC HDPR-31 is reported:

HDPR #1 Warning 182972 cells with INIT values are found without resets. Without a reset the INIT value will not be loaded during a partial reconfiguration.
To fix this issue: add a reset to each cell that can be held during and released after a partial reconfiguration.
The following is a list of cells (up to the first 15) with INIT values that need to have resets:

TOP/r_EG_IN_Buf_reg[0][0][0] (1'b0)
TOP/r_EG_IN_Buf_reg[0][0][10] (1'b0)
TOP/r_EG_IN_Buf_reg[0][0][11] (1'b0)
TOP/r_EG_IN_Buf_reg[0][0][12] (1'b0)

All of the listed FF have reset signals and INIT values, why are they still reported?


Because the RESET_AFTER_RECONFIG property is not optional for UltraScale devices, this DRC should not apply to UltraScale devices.

This DRC is disabled for UltraScale devices in Vivado 2015.3.
AR# 64688
Date 07/06/2015
Status Archive
Type General Article
  • Vivado Design Suite - 2015.1
Page Bookmarked