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AR# 64708

2015.2 Vivado - Module set as "Out of Context" for synthesis, is treated as a black box for behavioral simulation

Description

I have set an HDL module as "Out of Context (OOC) for synthesis. 

However, it is now also treated as a black box for simulation.

The elaboration for simulation indicates that the module is treated as a black box and the simulation shows the outputs of the module as undefined (x).

For Example:

Starting static elaboration

WARNING: [VRFC 10-122] my_mod remains a black-box since it has no binding entity
[/proj/project_1/project_1.srcs/sources_1/imports/Sources/top.vhdl:249]

WARNING: [VRFC 10-122] my_mod remains a black-box since it has no binding entity
[/proj/project_1/project_1.srcs/sources_1/imports/Sources/top.vhdl:255]

Completed static elaboration

Running behavioral simulation from Flow Navigator shows the outputs of my_mod as X.

Solution

the Simulation compile order is not returning the OOC file from the fileset:

get_files -compile_order sources -used_in simulation -of_objects [current_fileset -simset]

The get_files -compile_order code should work for stitching together files across OOC blocks and other HDL.

Until this is fixed, two ways to work around the issue are:

 

  • Unset the OOC designation when running simulation
  • Set the following parameter which will allow a unified fetch for OOC files.
set_param project.addBlockFilesetFilesForUnifiedSim 1
AR# 64708
Date Created 05/29/2015
Last Updated 06/30/2015
Status Active
Type Known Issues
Tools
  • Vivado Design Suite - 2015.1
  • Vivado Design Suite - 2015.2