UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 64718

UltraScale FPGA Gen3 Integrated Block for PCI Express (Vivado 2015.1) - Incorrect refclk_buf location for XCVU095 - FFVC2104, XCVU190 - FLGA2577 and XCVU125 - FLVC2104

Description

Version Found: v4.0 (Vivado 2015.1)
Version Resolved and other Known Issues: See (Xilinx Answer 57945)

When generating UltraScale FPGA Gen3 Integrated Block for PCI Express core for the following devices, the generated XDC file consists of incorrect refclk_buf locations.

  • XCVU095 - FFVC2104
  • XCVU190 - FLGA2577
  • XCVU125 - FLVC2104

Solution

This is a known issue to be fixed in the next release of the core.

Please correct the constraints as follows:

Note: The "Version Found" column lists the version the problem was first discovered. 

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.
Revision History:
06/02/2015 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
57945 UltraScale FPGA Gen3 Integrated Block for PCI Express - Release Notes and Known Issues N/A N/A
AR# 64718
Date Created 06/02/2015
Last Updated 06/26/2015
Status Active
Type Known Issues
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)